Problem when using BuildGates Synthesis tool. Pls help me!

Hi all,
I had a problem when I used BuildGates Synthesis tool. I import verilog file, timing library (.tlf) and do synthesize and optimize my design. But when I write to netlist it can't dissolve my design into std cells. In my netlist file, it also call many instance and map pin when I call in my top module.
Ex:
kenh8 A8(.th_clock(clk), .th_reset(th_reset), .clock(kenh8), .base(base)
, .data_adc(adc), .rptc_cntr(rptc_cntr), .pwm_pad_o(pwm_pad_o8),
.selsource(selsource8));
kenh7 A7(.th_clock(clk), .th_reset(th_reset), .clock(kenh7), .base(base)
, .data_adc(adc), .rptc_cntr(rptc_cntr), .pwm_pad_o mainclk U1(.clock(clk), .reset(th_reset), .kenh1(kenh1), .kenh2(kenh2),
.kenh3(kenh3), .kenh4(kenh4), .kenh5(kenh5), .kenh6(kenh6), .kenh7(kenh7), .kenh8(kenh8), .base(base), .rptc_cntr(rptc_cntr));
I also get schamtic from this tool and the connectivity is correct.
Pls help me solve this problem.
Thanks.