Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It is a matter of strong on polarization, nmos saturation is stronger than pmos, that is why they are preffered for draining current from an output rather than sourcing current toward an output.
Its due to the fact that NMOS's drain can go to 0V without affecting the Vgs...and similarly PMOS's drain can go to Vdd without affecting the Vgs... so we can have 0 to Vdd swing...
Usually we connect source of pmos to the Vdd, and the source of the Nmos to the ground, Do this to easily control current. If the bias voltage is high, Pmos is almost off, then Vout ~ Vdd => logic 1. And when the bias voltage is low, Nmos is off, then Vout ~ Gnd => logic is 0.
Regard.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.