Pipelining Techniques

pipelining techniques

1. What are the different Processor Pipelining Techniques?

2. What are the constraints to be taken into account while implementing a Pipelined Processor architecture?

Thanks in Advance!!

what is meant by pipelining techniques

hi,
as to architecture, I think you can read some books on it such as "computer architecture", etc.
and constraint on it, I dont think anything need be careful. becoz the way of ASIC implementation is RTL which means pipeline a bit.

pipelining

I do agree on the linuxluo comments.
once the architecture/concept settled down, what you only to do is using register to do RTL implementation.

pipeline def --- successive instructions in a program sequence will overlap in execution

processor pipeline ----

suppose processor sequence is

Instruction fetch --> Instruction decode and register fetch --> Execute --> memory access --> Register write back

Now here there r 5 stages right!!
so here a 4 stage pipeline can be followed as second instruction is dependent on the first one and third on the second i.e while executing the 5th instruction 1st instruction is done( 4 cycle's delay) but now it is in series suppose in the next cycle some new instruction set has come the second instrucion of the previous(i.e Instruction decode and register fetch) will be completed in the cuurent cycle.
so now here there was an initial latency but as successive instructions are done it is not waiting for the cuurent instruction to execute but doing the previous instrucion.

i hope u understood this!!

p s --> the above is purely based on an example, the real risc processor architecture may differ from above.

It is very important to steal time budget in pipeline design.

hai ,
for normal architecture will take two clock cycle for single instruction ( one for fetching and one for excution ) but in piepline architecture only one clock cycle is enough for both ( fetching and excution )

hey venkatesh,
few corrections
as u have given "normal architecture will take two clock cycle for single instruction" even when it is pipelined it requires 2 cycles for single instruction. Here while fetching next instruction the current exectuion is done. Here it is helpful for back to back instructions only.

well pipeline has its own adv and disadv.

Thanks & Regards

Individual instructions take their repective clock cycles to complete but after each clock cycle we will have output.

This works like a assembly line of car factory. Single car takes too long time to get manufactired but after each time slot we have a car manufactured.

Means work has been divided in different slots.

I think you can read some books on it such as "computer architecture", etc.
and constraint on it, I dont think anything need be careful. becoz the way of ASIC implementation is RTL which means pipeline a bit.

Pipelining is used not only in processor design but also in other digital designs for better performance. We need to add optimum number of stages to get the best performance benefit. Adding too many pipeline stages will add more latency and hence more performance degration.

hai eeeraghu,
thanks for for ur replay

Thanks alot for such a good information

Pipelining need not be only 5 stages.Each stage can be subdivided thus forming a super pipeline. Actually the more stages you divide the pipeline, the less is the gate delay in each stage and thus the clock frequency can be considerably reduced.Thus deeper pipeline leeds to better performance..

Added after 3 minutes:

Also there is a small pitfall in deeper pipelining. when a branch is encountered,the entire pipeline has to be flushed and reloaded with new instructions..One way to overcome this pitfall is using a multithreaded architecture

@ubna
Can you please explain a little bit about multithreaded architecture and how it can be helpful when branch is encountered in pipeline?

Hi bharat,

Multithreading:
A normal microprocessor can execute instuctions only in sequence. that is it can execute instructions in a program one by one and can switch to another program only if all the instructions in the current program are executed.A thread is nothing but a assembly language program. In a multithreaded processor, more than one program can be placed in the memory, and the processor can run the instructions of all the programs simultanoeusly by switching between threads for every instruction.In this way a process need not wait for the current process to finish thus increasing the performance of the processor. Another advantage here is that in normal processors, the processor does not do any work in the time taken for the next thread get started.But in multithreading this time is considerably reduced.

Multithreading with pipeline:
In an ordinary processor with pipeline if a branch is executed and if the branching need to take place, the instruction with the address in the branch need to be executed next. So the entire pipeline is flushed.After flushing the pipeline the no. of clock cycles spent for the next execution is equal to the no. of pipeline stages before the execution stage.So the processor does not produce any output for that many clk cycles.The no. of clock cycles wasted increases as the pipeline's depth. But in multithreaded architecture since the next instruction in the pipeline is that of another thread's only very few stages of the pipeline needs to be flushed, thus increasing the throughput of the processor.
In a mutithreaded pipeline
No. of clk. cycles waste=No. of pipe stages/no. of active threads

Another very important usage of multithreading is in interrupt handling..

After your explanation I deduced :
in a mulltithreaded app, each active threads needs its own stack. So the processor needs to swap context ( registries, status ) at each clock cycle.
How does the branch prediction works?

if the instruction execute in different clock cycles , how to deal with it.

'Instructions executing in different clock cycles' is a very different problem to tackle with..
One solution(but not effective) i know is by tracking those instructions..
i.e whenever an instruction with different clock cycle is encountered at the start of the pipeline, the control must carefully allow the subsequent instructionssuch that two instructions do not clash.This leads to the pipeline stages being idle for many clock cycles which leads to a slight decrease in the performance of the processor

This is a very large range question, it is very difficult to give out an answer in just few word.

Currently, the pipeline structures from some classic implementation is a hybrid of RISC/CISC/VLIW, supperscaler,

I think you can start from some papers on these pipeline and instruction set

Hennessy and Patterson's book 'Computer Architecture: a quantitative approach' is useful for you.
There is download links for serval editions in this forum.