Help me write a Verilog code for internal structure of glue logic

hello.......... in tha attached file, for the 2nd figure im unable to write a error free code. plz help me......

Re: verilog code needed

Post the code that you already wrote so that it will be easy to make corrections.

Re: verilog code needed

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.reg_set.all;


entity GLUE_LOGIC is

port(
-- INPUTS
clk : in std_logic;
add_bus : in std_logic_vector ( 3 downto 0 );
data_bus : in std_logic_vector ( 7 downto 0 );
hsync : in std_logic ;
vsync : in std_logic ;
pclk,en : in std_logic ;
acquire : in std_logic ;
reset : in std_logic;
-- ce : in std_logic ;
enable : in std_logic ;
-- load/run : in std_logic ;
irdy : in std_logic ;
-- OUTPUTS
we : out std_logic ;
ie : out std_logic ;
wrst : out std_logic ;
-- wclk : out std_logic ;
-- fifo_error : out std_logic ;
fifo_full : out std_logic ;
-- loa : out std_logic;
error,q : out std_logic;
acq_ack : out std_logic );

end GLUE_LOGIC;

architecture arch of GLUE_LOGIC is

attribute syn_preserve : boolean;
attribute syn_preserve of arch: architecture is true;

--- constant clk_period : time := 20 ns;

signal r_0,r_1,r_2,r_3,r_4,r_5 : std_logic_vector(7 downto 0);
signal r_6,r_7,r_8,r_9,r_10,r_11 : std_logic_vector(7 downto 0);
signal c0,c1,c2,c3,c4,c5,c6 : std_logic_vector(15 downto 0);
signal reg0,reg1,reg2,reg3,reg4,reg5 : std_logic_vector(15 downto 0);
signal load1,load2,load3,load4,load5,load6 : std_logic;
signal a,b,c,d,e,f,g,h,i,j,k,l,m,n : std_logic;
signal clk1,disable,disable1 : std_logic;

component and2
port ( vsync,acquire : in std_logic;
load1 : out std_logic);
end component and2;

component xor2
port ( q,r : in std_logic;
load : out std_logic);
end component xor2;

component or2
port ( x,y : in std_logic;
z : out std_logic);
end component or2;

component register_set
port(
addr_bus : in std_logic_vector ( 3 downto 0 );
data_bus : in std_logic_vector ( 7 downto 0 );
clk : in std_logic ;
rst : in std_logic;
enb : in std_logic ;
error : out std_logic;
r0_out,r1_out,r2_out,r3_out,r4_out,r5_out,r6_out,
r7_out,r8_out,r9_out,r10_out,r11_out : out std_logic_vector ( 7 downto 0 ) );

end component register_set;


begin

q <= disable;
-- load6 <= load16

U0 : and2 port map(vsync, acquire,load1);
U1 : register_set port map ( add_bus,data_bus,clk,reset,enable,error,
r_0,r_1,r_2,r_3,r_4,r_5,r_6,r_7,r_8,r_9,r_10,r_11);
U2 : xor2 port map (a, b,load2);
U3 : xor2 port map (c, d,load3);
U4 : xor2 port map (e, f,load4);
U5 : xor2 port map (g, h,load5);
U6 : xor2 port map (i, j,clk1);
U7 : xor2 port map (k, l,disable);
U8 : xor2 port map (m, n,disable1);
U9 : and2 port map (clk1,j,load6);

reg0 <= r_0 & r_1;
reg1 <= r_2 & r_3;
reg2 <= r_4 & r_5;
reg3 <= r_6 & r_7;
reg4 <= r_8 & r_9;
reg5 <= r_10 & r_11;


-- Indicates frame starting & Voffset
P1: process (hsync,load1,reg0)
variable c0_16 : std_logic_vector(15 downto 0);
variable load12 : std_logic;
variable load121 : std_logic;
begin
load12 := '0';
load121 := '0';
-- c0_16 := (others => '0');

if(load1 = '1') then
c0_16 := reg0;
elsif(hsync'event and hsync = '1') then
if(c0_16 /= 0) then
c0_16 := c0_16 - 1;
if(c0_16 = 1) then
load12 := '1';
elsif(c0_16 = 0) then
load121 := '1';
end if;
end if;
end if;
c0 <= c0_16;
a <= load12;
b <= load121;
-- o <= load122;
-- p <= load1221;

end process P1;

-- Voffset to Hoffset starting
P2: process (pclk,load2,reg2)
variable c1_16 : std_logic_vector(15 downto 0);
variable load13 : std_logic;
variable load131: std_logic;
variable acq,wrst_1 :std_logic;

begin
acq := '0';
load13 := '0';
load131 := '0';
wrst_1 := '0';
-- c1_16 := (others => '0');
if( load2= '1') then
c1_16 := reg2;
elsif(pclk'event and pclk = '1') then
if(c1_16 /= 0) then
c1_16 := c1_16 - 1;
if(c1_16 = 1) then
load13 := '1';
elsif(c1_16 = 0) then
load131 := '1';
acq := '1';
wrst_1 := '1';
end if;
end if;
end if;

c1 <= c1_16;
c <= load13;
d <= load131;
acq_ack <= acq;
wrst <= wrst_1;

end process P2;

-- Hoffset
P3: process (pclk,reg2,load3,clk1,disable)
variable c2_16 : std_logic_vector(15 downto 0);
variable load141,load14 : std_logic;

begin

load141 := '0';
load14 := '0';
-- c2_16 := (others => '0');


-- load141 := '0';
-- load14 := '0';
if( load3 = '1' or clk1 = '1') then
c2_16 := reg2;
elsif(disable = '1') then
c2_16 := (others => '0');

elsif(pclk'event and pclk = '1') then
if(c2_16 /= 0) then
c2_16 := c2_16 - 1;
if(c2_16 = 1) then
load14 := '1';
elsif(c2_16 = 0) then
load141 := '1';
end if;
end if;
end if;
c2 <= c2_16;
e <= load14;
f <= load141;

end process P3;

-- Converter Latency
P4: process (pclk,load4,reg4)
variable c3_16 : std_logic_vector(15 downto 0);
variable load151,load15 : std_logic;
-- variable enb : std_logic;

begin

load151 := '0';
load15 := '0';
-- enb := '0';
-- c3_16 := (others => '0');

if (load4 = '1') then
c3_16 := reg4;
elsif(pclk'event and pclk = '1') then
if(c3_16 /= 0) then
c3_16 := c3_16 - 1;
if(c3_16 = 1) then
load15 := '1';
elsif(c3_16 = 0) then
load151 := '1';
-- enb := '1';
end if;
end if;
end if;
c3 <= c3_16;
g <= load15;
h <= load151;
--- enabl <= enb;

end process P4;

-- Htotal
P5: process(pclk,load4,reg3)
variable c4_16 : std_logic_vector(15 downto 0);
variable load16,load161 : std_logic;

begin

load161 := '0';
load16 := '0';
-- c4_16 := (others => '0');

if (load4 = '1') then
c4_16 := reg3;
elsif(pclk'event and pclk = '1') then
if(c4_16 /= 0) then
c4_16 := c4_16 - 1;
if(c4_16 = 1) then
load16 := '1';
elsif(c4_16 = 0) then
load161 := '1';
end if;
end if;
end if;
c4 <= c4_16;
i <= load16; -- clk
j <= load161;
-- load6 <= load16;
end process P5;

-- Vtotal
P6: process (load6,load2,reg5)
variable c5_16 : std_logic_vector(15 downto 0);
variable load171,load17 : std_logic;

begin

load171 := '0';
load17 := '0';
-- c5_16 := (others => '0');

if (load2 = '1') then
c5_16 := reg5;
elsif(load6'event and load6 = '1') then
if(c5_16 /= 0) then
c5_16 := c5_16 - 1;
if(c5_16 = 1) then
load17 := '1';
elsif(c5_16 = 0) then
load171 := '1';
end if;
end if;
end if;
c5 <= c5_16;
k <= load17; -- disable
l <= load171;

end process P6;

-- Htotal to generate control signals
P7: process (pclk,load5,reg3)
variable c6_16 : std_logic_vector(15 downto 0);
variable load181,load18 : std_logic;

begin

load181 := '0';
load18 := '0';
-- c6_16 := (others => '0');

if (load5 = '1') then
c6_16 := reg3;
elsif(pclk'event and pclk = '1') then
if(c6_16 /= 0) then
c6_16 := c6_16 - 1;
if(c6_16 = 1) then
load18 := '1';
elsif(c6_16 = 0) then
load181 := '1';
end if;
end if;
end if;
c6 <= c6_16;
m <= load18; -- disable1
n <= load181;

end process P7;

-- Generating control signals
P8: process(load5,disable1,irdy)
variable we_1 : std_logic;
variable ie_1 : std_logic;
-- variable wclk_1 : std_logic;
variable fifo_full_1 : std_logic;
variable fifo_error : std_logic;
begin
we_1 := '0';
ie_1 := '0';

fifo_full_1 := '0';


if (load5 = '1') then
we_1 := '1';
ie_1 := '1';
-- wclk_1 := '0';
-- wait for (clk_period/2);
-- wclk_1 := '1';
-- wait for (clk_period/2);
elsif(disable1 = '0') then
we_1 := '0';
ie_1 := '0';
-- wclk_1 := '0';
fifo_full_1 := '0';
-- fifo_error_1 := '0';
elsif(irdy = '1') then
fifo_full_1 := '1';
else
fifo_full_1 := '0';
-- end if;
end if;
we <= we_1;
ie <= ie_1;
-- wclk <= wclk_1;
fifo_full <= fifo_full_1;

end process p8;

-- P9: process
-- variable wclk_1 : std_logic;
-- begin
-- wclk_1 := '0';
-- if( enabl = '1') then
-- wclk_1 := '0';
-- wait for (clk_period/2);
-- wclk_1 := '1';
-- wait for (clk_period/2);
-- end if;
-- wclk <= wclk_1 ;
-- end process P9;

end arch;




for the register_set component, i just wrote a program send the data into d registers..........

Added after 30 minutes:

actually i wrote dis code in vhdl. but i need it in verilog. i dont hav much knowledge in verilog..... plz do help me....