A
ahmadagha23
Guest
subprogram = ambiguos modelsim
hi,
I tried to compile a vhdl code (from xilinx.com) which contain following line:
"if rst = '1' or std_logic_vector(no_bits_sent) = "1010" then "
by modelsim5.6 i received following error message:
"Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'."
but activhdl5.1 compiled it successfully. Do you know why and what is the difference between modelsim and activhdl in these situations?
regards
hi,
I tried to compile a vhdl code (from xilinx.com) which contain following line:
"if rst = '1' or std_logic_vector(no_bits_sent) = "1010" then "
by modelsim5.6 i received following error message:
"Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'."
but activhdl5.1 compiled it successfully. Do you know why and what is the difference between modelsim and activhdl in these situations?
regards