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What does combinatorial loop warning mean?

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I am using Xilinx ISE 9.1 to program Spartan3.

I got the following message : the following signal(s) form a combinatorial loop:

POL_TEMP.

What this means?

Thanks
 

the following signal(s) form a combinatorial loop

That warning message means your design has combinatorial logic with an output feeding back to the input, forming a loop. The result is usually a latch or oscillator. Most FPGA designers want to avoid such things, so the synthesis tool warns you.
 
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