modelsim62c
Member level 2
localparam in vhdl
I want to port some VHDL RTL files to Systemverilog (for synthesis.)
There are a few VHDL subtype-declarations I don't know how to write (directly) in Systemverilog:
positive, negative, natural
Now, I know i can just convert this to 'int', but I'd like to preserve the restricted-range of the original...is this possible?
For now, I've just put in 'dummy placeholders'
Is there a better way to do this?
Code:
signal my_sig1, my_sig2 : natural range 0 to INIT_CYCLES; --I want to port some VHDL RTL files to Systemverilog (for synthesis.)
There are a few VHDL subtype-declarations I don't know how to write (directly) in Systemverilog:
positive, negative, natural
Now, I know i can just convert this to 'int', but I'd like to preserve the restricted-range of the original...is this possible?
For now, I've just put in 'dummy placeholders'
Code:
// imprecise substitute for VHDL's natural/positive/negative
typedef int positive; //
typedef int natural;
typedef int negative;
// std_replacement for VHDL's 'boolean' variable
typedef bit boolean;
localparam boolean false = 1'b0;
localparam boolean true = 1'b0;Is there a better way to do this?