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About the degree of parallelism of a time-interleaved ADC

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wilco

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Hi:

It's very simple:

I can't understand why in fig 3 of the well known paper "A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter" of Waltari and Sunamen, where the authors study the effect of the degree of parallelism on the current consumption for a 10 bit ADC, the linear part of the curve ( when the SR limitation is dominant) is equal for 2 and 4 channels(B=1,M=2 and B=1,M=4).In that figure, the 2 curves overlap in the SR range..

I've been looking different ref's, but I don't find an explicit answer to my question.

So, is always the current consumption caused by the SR limitation independent from the number of channels in a time-intyerleaved ADC ??

This is important for me because this shape of the curve makes a 2-channel ADC the best option under certain corner frequency.

Thanks a lot for ur answers
 

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