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how to design a 74HC245 using verilog?

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vonzhaoqun

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74hc245 verilog

i try many times,but not sucess. :( can you help me? thanks
 

74hc245 tutorial

Hi,

Here is alot of standard 74xxx models, but i do not try any :

**broken link removed**


Here is tutorial from Actel with lot of examples :

**broken link removed**
 

i think the program should be like this

assign output=control?input:Z;

if u wanna use output enable then make it

assign output=(control & OE)?input:Z;
 

papyaki:
thank you very much!


gauiver:
it is most like a 74hc244,but thank u


any good idea are welcome
 

if you target actual design, you can instantiate Tri-state buffer from the target FPGA and do the required connection. I see a lot of xilinx application do so and do not use HDL description. to avoid different synthesizer methodology.
 

Tetra:
thank u,when i try it in vhdl,i got the right result,but i still can not do it in verilog,can u say more about "avoid different synthesizer methodology"?


vonzhaoqun
 

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