jinal patel
Full Member level 1
what is the exact defination of clock skew related to digital /VLSI system?
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Shans60 said:Consider just two flops connected via a combinational circuit .. if the flop1 responds to the rising edge of the clock cycle then the flop must respond to the next rising edge but due to some interconnect delay it will not respond to rising edge exactly.. this can be positive or negative... both must be taken care as they have their effects in circuits...
jinal patel said:what is the exact defination of clock skew related to digital /VLSI system?