Shift register problem.

Hi Group

I am about designing an SIRCS decoder realized in FPGA via VHDL, but it seems, that i have a problem with a shift register.

The code below is a modified version of what i am trying to implement, in the code below i am allways trying to put a logical one into the shift register, but when i am reading out svIR_SIRCS_DATA it is aways ZERO not bits set, can any body tell me what i am douing wrong ?

Below the code:

--IR SIRCS.
IR_SIRCS: process (eOSC_TIMING)
begin
if (eOSC_TIMING' event and eOSC_TIMING = cTRUE) then

-- Receive and handle IR SIRCS signal.
svIR_SIRCS_DATA(0) := svIR_SIRCS_DATA(1) ;
svIR_SIRCS_DATA(1) := svIR_SIRCS_DATA(2) ;
svIR_SIRCS_DATA(2) := svIR_SIRCS_DATA(3) ;
svIR_SIRCS_DATA(3) := svIR_SIRCS_DATA(4) ;
svIR_SIRCS_DATA(4) := svIR_SIRCS_DATA(5) ;
svIR_SIRCS_DATA(5) := svIR_SIRCS_DATA(6) ;
svIR_SIRCS_DATA(6) := svIR_SIRCS_DATA(7) ;
svIR_SIRCS_DATA(7) := svIR_SIRCS_DATA(8) ;
svIR_SIRCS_DATA(8) := svIR_SIRCS_DATA(9) ;
svIR_SIRCS_DATA(9) := svIR_SIRCS_DATA(10) ;
svIR_SIRCS_DATA(10) := svIR_SIRCS_DATA(11) ;
svIR_SIRCS_DATA(11) := '1' ;
end if;

end process;


Thanks alot for your help in advance.


Best regards
René

Hi,

It seems that the problem with eOSC_TIMING signal
it may not change to cTRUE.
Try the same code with a signal that you can force with a clock.

Regards.

all it is is shift register, with eOSC_TIMING acting as a clock, another word check you testbench can you see clock signal comming to eOSC_TIMING?