What is the operation principle of ROM, SRAM and DRAM cell?

thanks................

Re: What is the operation principle of ROM, SRAM and DRAM ce

Digital circuit could be implemented in a variety of ways one of whch is using a Rom which is a fixed AND and fixed OR Array. SRAMs and DRAMS, on the other hand are two types of Random Access Memories. In the former The informathion is stored Statically which means it does not need to be refreshed but in the latter the information has to be refreshed periodically in order to be sustained. This is because the information is stored as voltages in capacitors which tends to discharge with time.

Hope this got u off the hook buddy!

Basically, a RAM cell is nothing but a bi-stable - like circuit. You can set or reset the state, depending on the bit reqd. SRAM and DRAM differs in the way charge is stored..

Re: What is the operation principle of ROM, SRAM and DRAM ce

i cant find information about bjt sram on net.......please if u can find help me out

Re: What is the operation principle of ROM, SRAM and DRAM ce

The differeence between SRAM and DRAM is the way of storing the data in it.. In DRAM data is stored through capacitors by cahrging and diacharging it. in SRAM the accesing of data depends on word and bit lines.. When wordline is low SRAM is in standby mode, when wordline is high den access transistors are on and we can perform write and write operations. In Dram read and write are done through capacitors. This two can be acessed randomly..
In ROM we can only read sequentily..

Re: What is the operation principle of ROM, SRAM and DRAM ce

Forget 'ad_11's reply.

ROM is memory which can contain information which is non-volatile. This means it is retained even if the power is removed. It can be implemented in many ways but the most common are fusible links, mask programming and floating capacitor cells. fusible links are just that, an array of silicon links that can be selectively broken by passing current through them. They operate very quickly but the physical size of the link structure makes them unsuitable for very large ROMs. Mask Programmed ROM is memory pre-programmed by the manufacturer, most commonly seen in things like character generators or where the ROM is mass produced. Floating cell is a ROM where the logic state is stored on a capacitor embedded in the silcon. These are sometimes called OTP memory as they are manufactured in an empty state and programmed later. they have no mechanism for erasing the contents.

SRAM is volatile memory, it loses it contents when the power is removed. The logic state is saved in bi-stable circuits, one per bit, inside the device. The logic state is changed by 'flipping' the bi-stable state. As the bi-stable is made form several components, SRAM is more complicated to fabricate and occupies more silicon area then other types so it is not commonly used as a large capacity store. It has a major advantage that with the exception of during writing and reading, there are no signal changes inside the device so it's current consumption is very low.

DRAM is in principle like ROM but instead of the floating cell being relatively large and designed to hold charge for decades, it is designed to be written or read very quickly. It is a volatile memory and to keep the time needed to write the cell as short as possible, it is made very small and typically discharges in a fraction of a second. To ensure the memory retains its contents, it is read and rewritten either with new contents or it's original contents every few milliseconds. This process is called 'refreshing' and can be done externally by accessing the device or by an internal read and write process. The small storage element and simple read/write circuit make this kind of memory suitable for large scale storage. The constant processing on every cell makes them relatively high in power consumption but the large capacity makes the 'per cell' efficiency very high.

All these memories store bits in an array. The array is rectangular but not necessarily square and each cell is accessed by an X and Y row and column coordinate. The coordinates are entered externally on the address lines. Some memories use parallel addressing where all the address lines are presented simultaneously, some are multiplexed (DRAMS in particular) where the X and Y coordinates share the same pins and are latched into the device by control signals, some are serial (SPI, I2C, Microwire...) where the bits are shuffled into one pin on a timed basis.

The read/write control and enable signals can be either polarity, it depends on the manufacturer and bus type. All these devices can be randomly accessed. Random in this sense means any address at any time rather than having to read the cells in a particular order.

Brian.