Clock Synchronization

fpga clock synchronization

Hi,

I've a problem with Altera FPGA based design. I'm workin on a processor-based board which uses the Cyclone FPGA and an IP core processor. Now the only other peripherals on the board are SDRAM, FLASH, MIL1553. The processor has built-in peripherals such as UART, Ethernet. The function of the FPGA is to conrtol the processor.

The problem faced is in clock synchronization. The internal PLL of the processor generates the core clock as well as SDRAM and SRAM clocks which are 1/4th and 1/8th of the core clock. The core clock is 200MHz.

The FPGA houses the logic to control the processor a main FSM, address decode logic, SDRAM controller..etc. I need to sync the FPGA FSM clock with the SRAM clock from the processor. The SRAM o/p from the processor is connected to the FPGA and the way I sync it is by passing the SRAM clock as the clock input to a D-FF and the FPGA clock of 25MHz to the D i/p. The ouput should be a clock that is in synch with the SRAM clock.

But what I get is a logic '1' o/p and no clock o/p. The SRAM clock is 25MHz and the FPGA logic clock is also 25MHz. Is it possible to sync the clocks or is there any other method of sync?? Can I use a 50MHz clock (SDRAM clock) from the processor to sync this FPGA clock??

sample clock fpga clock

From your description, it sounds like the FPGA clock is leading the SDRAM clock by some amount. Since you receive a constant logic "1", it sounds like you are not close to a clock edge. Therefore, it seems that all you require is to take the SDRAM input and double buffer it with two flops in the FPGA clock domain. This is usually the preferred method. You really cannot sync two clocks that are at an arbitrary phase relationship unless you use a PLL or DLL.

However, in cases like yours where the frequencies are the same, you do not need to sync. All you need to do is to insure that you can pass data between the two clock domains. We have done numerous FPGAs over the years that require 5-10 different clocks at different phase relationships to a master clock. In order to pass the data, we use a meta circuit. The meta circuit either passes the data using the rising edge of the sample clock or the falling edge of the sample clock. We use which ever one gives that best timing margins for that particular clock. Often either clock edge works just fine. However, when we are very clock to a clock transition, switching to the other clock edge always clears up the issues. Within the meta circuit, we set our timing fairly tight so that we can make timing from the negative edge of the sample flop to the rising edge of the next flop. That insures that all downstream logic can use the rising edge of the clock and we do not have to switch over entire sections of the FPGA.

fpga to data clock synchronization

Yes, what I want to do is to phase synch between the SRAM and FPGA clocks. This is required for proper operation of the processor core. Well, the Cyclone has two PLLs and I was using them both to generate the other frequences, but i guess i can generate another clock output which is in-phase with the SRAM clock using one PLL.

Thanks for the input anyways!

processor and fpga clock sync

Can't you use the same clock that goes to SRAM/SDRAM to run your FPGA ? This way you won't need to worry about synchronization, once you have established the clk skew required to meet setup/hold at IOs.