design works well at fpga but fails in real chip?

design problem

any body encounter the kind of problem that your design works well at
fpga but fails in real chip? can you tell the story?

FPGA Problem

I have experience some FPGA problems when I started out as graduate engineer. Some of the problems are to do with mestability and timing issues. When debugging the FPGA, the design always have test points for the internal signals and these are linked up to the test pins in the PCB. Most of time I debug the real chip via this method (using oscilloscope and logic analyser) and this seem to gave me a better understanding of the problem. The problem experience in real-life, I usually study the inputs to the device and simulate the scenario in Modelsim.

The company I work for do not follow a proper verification plan. They rather programme the device (mostly one-time programmable) and test it in hardware so the design is not fully tested in simulation. Some of the worst case is not considered.

Other times, I am fixing other people's bugs such as optimising their code and correcting it to comply with the specifications. Sometimes it is frustrating, when looking at several hundreds lines of code and the documentation is not provided but I gradually overcome this obstacle. When I start writing VHDL code, I sometimes draw block diagrams and determine the number of flip-flops and combinatorial logic used for the design. Sometimes it can be longwinded.

My company just recently brought in HDL designer so I am currently learning how to use the software for the next project.

One problem I have experience recently when connecting another IC to the FPGA. Both being powered by two different voltage lines. When the FPGA power down, I found out the FPGA is still being powered by the other IC due to the connection. This is maily due to the power supply not being grounded properly but in my case, I use a tristate buffer to tristate the IC output to the FPGA.

Eziggurat

When you say "works well at fpga but fails on real chip", I suppose you mean that it works in your functional simulation. I would check the timing reports from the synthesis and par tool (get an eye on timing analisys coverage) . If these figures are valid check asynchronous interfaces as external interfaces, signals between different clocks domains, resets...

Good luck

Hi

For design to work in FPGA place and route simulation is adequate.

From FPGA to ASIC:
1) Do tons of simulation.
2) Cross check the design
3) Do not ignore any warnings

Best of luck