How to design a clock divider with little resources?

please tell me how to design a clock divider with less number of resources

clock divider

simplest clock divider is a d flip flop. realistically speaking, it depends on period and dutycycle u want for your output clock.

clock divider

Can u plz tell me what is the division ratio u r looking for and what is the duty cycle requirement.
Sumit

Re: clock divider

the clock divider design has two important issue.
One is duty cycle.
The other is no glitch.

The attached is SNUG paper about clock divider.

Re: clock divider

There is no simple response for that question.
Base method is based on series of the d-flop's aech for dividing by factor of two. It is the worst method but sometimes is useful (slow clock or in CPLD's)
If you need fine dividing with precise duty factor you can use Digital Clock Manager block which is included in many types of the FPGA (but not all factors are possible)
In some Xlilinx FPGA each LUT can be used as shift registers. Proper initialization of the shift register as cyclic register with proper initial values for the every bit makes some interesting clock divider with many possible divide and duty factors (and it takes only one LUT per up to divide by 16 factor). This shift registers can be connected together to form bigger divide factors.

bis

Re: clock divider

how fast is your circuitry wanna to be? what is output of clock divider?

Re: clock divider

Sorry, the file is coming.

Re: clock divider

tahnks

Re: clock divider

thank you..

Re: clock divider

Simply use a counter and internal clock signal.if the counter reaches the max value make it zero and invert the signal clock.

at last give the internal sgnal clock to output clock.