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Help:Canceling the spikes of current mirror output current

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mohazaga

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Hi ,,,
the following ckt and output signal descripe the use of beta-multiplier as current source for SCL . As input signal to SCL is a pulse 0-1 volt with 1n width ,2n period (vin2 revers vin1). The current source sinked by SCL has a spikes as clear in output waveform (I3). Why? and how to solve?
thanks
The CKT , Wn2=53*220n Ln2=2*180n
https://obrazki.elektroda.pl/44_1176386680.jpg
Output signal (currents)
https://obrazki.elektroda.pl/95_1176386865.jpg
waiting
 

Hi
I think your problem is "clock feed through".
connect a capacitor to gate of M5. (cap must be between gate of M5 and Gnd)
maybe it reduce spikes.
regards
 

Well, if you put a big cap on M5, you might be able to reduce the amplitude of the spikes, but at the same time you increase the time constant for that node settling. You may run into a situation where bursts of activity on SCL could cause a low frequency change on your reference circuit.

One possible solution would be to build a buffer to put before the inputs that would limit the low voltage swing on the inputs -- that way you don't get the spikes on M5 during switching.
 

Re: Help:Canceling the spikes of current mirror output curre

Hi ,,,

Could u explain further? and is the values of W/L has any effect over that?

or if we put diod connected CMOS on drain of M5 can reduce the spikes?!
thanks

Added after 3 hours 36 minutes:

Hi ,,,
I try that solution but the spikes still there ?
thanks
 

Hi
I don't know more about clock feed through in scl circuits.
clock feed through is division of input clock across Cgs1, Cdg5 and Cg5.
I think large cap in gate of M5 can reduce it but yes I think it can reduce speed of SCL.
But if vin2 is reverse of vin1 then we must have no clock feed through or very little.
regards
 

Re: Help:Canceling the spikes of current mirror output curre

Hi ,,,
I add another stage of scl to see the effect of it over but the current at next current mirror stage get worst wich effect the out out of the 2nd SCL. ( with same input pulse mention early).
just see I1,I2,I3 & I4 in next figures.
I post bothe the ckt and the output signal
could u help please ?
thanks
9_1176610996_thumb.jpg

https://obrazki.elektroda.pl/9_1176610996.jpg
77_1176611074_thumb.jpg

https://obrazki.elektroda.pl/77_1176611074.jpg
 

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