VHDL write() function in std_textio

HI!

Can anyone please help me with write() function. I would like to make a results file, the problem is that when I use te function the data are writen in 1 line but I would like to write the result in cascasde like this

in_1 in_2 out
x y z
x1 y1 z1

In fact I am searching for new line (\n) attribute like in C++

any idea?

Now I use this sintax

write(TX_OUT,string'(" in_1" & & "in_2" & & "out"));
writeline(results, TX_OUT);
write(TX_OUT, in_1_var);
write(TX_OUT, in_2_var);
write(TX_OUT, out_var);
writeline(results, TX_OUT);



TNX bart

std_logic_vector to string

Do not use this libraries as they are not standard.

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Eziggurat



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
library unisim;

ENTITY dct_idct_tb IS
generic(
log_file1: string := "input_data.txt";
log_file2: string := "output_data.txt"
);
END dct_idct_tb;

ARCHITECTURE HTWTestBench OF dct_idct_tb IS

file l_file1: text open write_mode is log_file1;
file l_file2: text open write_mode is log_file2;


constant SIMULATION_DURATION : TIME := 20 us;

COMPONENT dct_idct
PORT (
clk : in std_logic;
rst : in std_logic;
xin : in std_logic_vector(7 downto 0);
idct_2d : out std_logic_vector(7 downto 0)
);
END COMPONENT;


-- procedure to print messages to stdout
PROCEDURE print(s: IN STRING) IS

VARIABLE l: line;

BEGIN

write(l, s);
writeline(output,l);

END print;

-- print string to a file
procedure print_file(file out_file: TEXT;
new_string: in string) is

variable l: line;

begin

write(l, new_string);
writeline(out_file, l);

end print_file;



-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;


SIGNAL clk_source : std_logic;
SIGNAL clk_en : std_logic;
SIGNAL rst_source : std_logic;
SIGNAL xin_source : std_logic_vector(7 downto 0);
SIGNAL idct_2d_source : std_logic_vector(7 downto 0);


BEGIN
UUT : dct_idct
PORT MAP (clk => clk_source,
rst => rst_source,
xin => xin_source,
idct_2d => idct_2d_source);


clock_process: process
begin
loop
clk_source <= '0';
wait for 5 ns;
clk_source <= clk_en;
wait for 5 ns;
end loop;
wait;
end process;


reset_process: process
begin
rst_source <= '1', '0' after 20 ns;
wait;
end process;


data_process: process
begin

xin_source <= X"28", X"21" after 25 ns,
X"21" after 35 ns, X"16" after 45 ns,
X"1A" after 55 ns, X"28" after 65 ns,
X"24" after 75 ns, X"1A" after 85 ns,
X"2B" after 95 ns, X"1A" after 105 ns,
X"21" after 115 ns, X"16" after 125 ns,
X"1D" after 135 ns, X"2B" after 145 ns,
X"16" after 155 ns, X"24" after 165 ns,
X"2B" after 175 ns, X"28" after 185 ns,
X"13" after 195 ns, X"24" after 205 ns,
X"24" after 215 ns, X"21" after 225 ns,
X"0F" after 235 ns, X"1A" after 245 ns,
X"24" after 255 ns, X"2B" after 265 ns,
X"1A" after 275 ns, X"21" after 285 ns,
X"1D" after 295 ns, X"1D" after 305 ns,
X"13" after 315 ns, X"04" after 325 ns,
X"21" after 335 ns, X"21" after 345 ns,
X"1D" after 355 ns, X"1A" after 365 ns,
X"0F" after 375 ns, X"21" after 385 ns,
X"1A" after 395 ns, X"0A" after 405 ns,
X"24" after 415 ns, X"21" after 425 ns,
X"21" after 435 ns, X"1A" after 445 ns,
X"16" after 455 ns, X"1D" after 465 ns,
X"1A" after 475 ns, X"0C" after 485 ns,
X"21" after 495 ns, X"28" after 505 ns,
X"1D" after 515 ns, X"1A" after 525 ns,
X"21" after 535 ns, X"0C" after 545 ns,
X"0C" after 555 ns, X"04" after 565 ns,
X"1A" after 575 ns, X"21" after 585 ns,
X"1D" after 595 ns, X"16" after 605 ns,
X"0C" after 615 ns, X"04" after 625 ns,
X"08" after 635 ns, X"00" after 645 ns,
X"28" after 655 ns, X"21" after 665 ns,
X"21" after 675 ns, X"16" after 685 ns,
X"1A" after 695 ns, X"28" after 705 ns,
X"24" after 715 ns, X"1A" after 725 ns,
X"2B" after 735 ns, X"1A" after 745 ns,
X"21" after 755 ns, X"16" after 765 ns,
X"1D" after 775 ns, X"2B" after 785 ns,
X"16" after 795 ns, X"24" after 805 ns,
X"2B" after 815 ns, X"28" after 825 ns,
X"13" after 835 ns, X"24" after 845 ns,
X"24" after 855 ns, X"21" after 865 ns,
X"0F" after 875 ns, X"1A" after 885 ns,
X"24" after 895 ns, X"2B" after 905 ns,
X"1A" after 915 ns, X"21" after 925 ns,
X"1D" after 935 ns, X"1D" after 945 ns,
X"13" after 955 ns, X"04" after 965 ns,
X"21" after 975 ns, X"21" after 985 ns,
X"1D" after 995 ns, X"1A" after 1005 ns,
X"0F" after 1015 ns, X"21" after 1025 ns,
X"1A" after 1035 ns, X"04" after 1045 ns,
X"24" after 1055 ns, X"21" after 1065 ns,
X"21" after 1075 ns, X"1A" after 1085 ns,
X"16" after 1095 ns, X"1D" after 1105 ns,
X"1A" after 1115 ns, X"0C" after 1125 ns,
X"21" after 1135 ns, X"28" after 1145 ns,
X"1D" after 1155 ns, X"1A" after 1165 ns,
X"21" after 1175 ns, X"0C" after 1185 ns,
X"0C" after 1195 ns, X"04" after 1205 ns,
X"1A" after 1215 ns, X"21" after 1225 ns,
X"1D" after 1235 ns, X"16" after 1245 ns,
X"0c" after 1255 ns, X"04" after 1265 ns,
X"08" after 1275 ns, X"00" after 1285 ns,
X"28" after 1295 ns, X"21" after 1305 ns,
X"21" after 1315 ns, X"16" after 1325 ns,
X"1A" after 1335 ns, X"28" after 1345 ns,
X"24" after 1355 ns, X"1A" after 1365 ns,

X"2B" after 1375 ns, X"1A" after 1385 ns,
X"21" after 1395 ns, X"16" after 1405 ns,
X"1D" after 1415 ns, X"2B" after 1425 ns,
X"16" after 1435 ns, X"24" after 1445 ns,
X"2B" after 1455 ns, X"28" after 1465 ns,
X"13" after 1475 ns, X"24" after 1485 ns,
X"24" after 1495 ns, X"21" after 1505 ns,
X"0F" after 1515 ns, X"1A" after 1525 ns,
X"24" after 1535 ns, X"2B" after 1545 ns,
X"1A" after 1555 ns, X"21" after 1565 ns,
X"1D" after 1575 ns, X"1D" after 1585 ns,
X"13" after 1595 ns, X"04" after 1605 ns,
X"21" after 1615 ns, X"21" after 1625 ns,
X"1D" after 1635 ns, X"1A" after 1645 ns,
X"0F" after 1655 ns, X"21" after 1665 ns,
X"1A" after 1675 ns, X"04" after 1685 ns,
X"24" after 1695 ns, X"21" after 1705 ns,
X"21" after 1715 ns, X"1A" after 1725 ns,
X"16" after 1735 ns, X"1D" after 1745 ns,
X"1A" after 1755 ns, X"0C" after 1765 ns,
X"21" after 1775 ns, X"28" after 1785 ns,
X"1D" after 1795 ns, X"1A" after 1805 ns,
X"21" after 1815 ns, X"0C" after 1825 ns,
X"0C" after 1835 ns, X"04" after 1845 ns,
X"1A" after 1855 ns, X"21" after 1865 ns,
X"1D" after 1875 ns, X"16" after 1885 ns,
X"0C" after 1895 ns, X"04" after 1905 ns,
X"08" after 1915 ns, X"00" after 1925 ns,
X"28" after 1935 ns, X"21" after 1945 ns,
X"21" after 1955 ns, X"16" after 1965 ns,
X"1A" after 1975 ns, X"28" after 1985 ns,
X"24" after 1995 ns, X"1A" after 2005 ns,
X"2B" after 2015 ns, X"1A" after 2025 ns,
X"21" after 2035 ns, X"16" after 2045 ns,
X"1D" after 2055 ns, X"2B" after 2065 ns,
X"16" after 2075 ns, X"24" after 2085 ns,
X"2B" after 2095 ns, X"28" after 2105 ns,
X"13" after 2115 ns, X"24" after 2125 ns,
X"24" after 2135 ns, X"21" after 2145 ns,
X"0F" after 2155 ns, X"1A" after 2165 ns,
X"24" after 2175 ns, X"2B" after 2185 ns,
X"1A" after 2195 ns, X"21" after 2205 ns,
X"1D" after 2215 ns, X"1D" after 2225 ns,
X"13" after 2235 ns, X"04" after 2245 ns,
X"21" after 2255 ns, X"21" after 2265 ns,
X"1D" after 2275 ns, X"1A" after 2285 ns,
X"0F" after 2295 ns, X"21" after 2305 ns,
X"1A" after 2315 ns, X"04" after 2325 ns,
X"24" after 2335 ns, X"21" after 2345 ns,
X"21" after 2355 ns, X"1A" after 2365 ns,
X"16" after 2375 ns, X"1D" after 2385 ns,
X"1A" after 2395 ns, X"0C" after 2405 ns,
X"21" after 2415 ns, X"28" after 2425 ns,
X"1D" after 2435 ns, X"1A" after 2445 ns,
X"21" after 2455 ns, X"0C" after 2465 ns,
X"0C" after 2475 ns, X"04" after 2485 ns,
X"1A" after 2495 ns, X"21" after 2505 ns,
X"1D" after 2515 ns, X"16" after 2525 ns,
X"0C" after 2535 ns, X"04" after 2545 ns,
X"08" after 2555 ns, X"00" after 2565 ns;

wait;
end process;


writing_input_data: process

begin
wait for 20 ns;
loop
if xin_source /= X"00" then

print_file(l_file1, hstr(xin_source));
end if;
wait for 10 ns;
end loop;
wait;
end process;

writing_output_data: process

begin

wait for 1885 ns;

loop

if idct_2d_source /= X"00" then
print_file(l_file2, hstr(idct_2d_source));
end if;
wait for 10 ns;
end loop;

wait;

end process;



process
begin

-- enable clocks
clk_en <= '1';
wait for SIMULATION_DURATION;

-- disable clocks
clk_en <= '0';

-- report end of simulation
print("Simulation complete...");
print(" ");

-- stop simulation
assert false
report "Simulation Complete (This is not a failure.)"
severity failure;
wait;

end process;



END HTWTestBench;