is it microstrip or stripline?

hi.

in this layer stack:



the traces on the L3, are they microstrip or stripline?

anyway, is it a good idea to route high speed signals on it? (DDR400)

If I say to the protel, that i want 60 ohm traces, it calculates a value for width. is it correct?

A signal trace on a layer between two planes will be a stripline - it doesn't matter if the plane is GND or VDD. DDR400 signals could be routed on L3. You would be better off swapping the VDD and GND layers to put the critical signals between two GND layers.

Yes, Protel calculates the width to satisfy the impedance rule.

As a separate observation, the stackup you have in your illustration is unbalanced. The board from such a stackup may warp after fabrication because of the unbalanced copper layers. You would be better off mechanically to make this an 8 layer board with another plane and another signal layer (e.e. Top-GND-S1-GND-VDD-S2-GND-Bottom).

Hi,

A signal between a couple of planes is always routed as STRIPLINE, in your case

L2------------------------- (GND) <-- ground plane
200um core
L3------------------------- (signals) <-- Stripline signal
800um prepreg
L4------------------------- (VDD) <-- power plane

MICROSTRIP is when you have only one reference plane, like upper trace (L1) or lower trace (L6) on your PCB,

When you say high speed signals, what do you really mean? speed rate? MTs? are they differential or single ended? control or data signals?

Also remember that traces at high speeds behave like transmission lines, with all their effects (mismatch terminations, rise time degradation, Crosstalk, ISI, ringing, overshoots/undershoots, operation modes, etc).

As I know, memory is always differential, if this is your case, cheers to you, differential has many signal integrity advantages than single ended. but you need to understand trade offs and routing restrictions and follow some rules of thumb when designing your PCB. (it's good to see that for high speeds like you said, you have kept ground and power planes directly adjacent).

Eric Bogatin, Howard Johnson and Stephen Hall SI books are very good references on this topics.

On your final question about your tool (honestly, I don't know how it works) but, one way to calculate Z0 is using formulas for symmetric or offset striplines (handy formulas comes on Hall and Johnson books) they use widths, heights, permittivity and thickness for your calculations.

A second way of calculating differential or common impedance is using a 2D field solver.

- jc

if i swap the gnd and vdd, then there will not be a contious reference plane for the L6, because the VDD layer has to be in so many pieces.

thats another thing why i am asking stripline?

the VDD can not be continous.

in your 8 layer stackup the S2 would be between a continous GND and a not continous VDD planes.
Or I must make it continous?

Mechanical Unbalance: if i put GND copper pour on L3, maybe it helps. doesnt it?


the speed is 400MTs but not differential.

Even if VDD is a split plane, traces on L3 are still striplines in your example.

GND fills on L3 would help the copper imbalance problem. However, you would need to use care about the spacing between the copper fill and critical traces. The presence of those fills will affect trace impedance if the trace is too close to the fill.

You are correct that a trace should not run over a split in a plane if that plane is the only reference for the trace. Return current would be forced to find a path that would diverge it from the signal trace. You want a return path that is directly under the signal path. In the both the stackups discussed here, there is at least one continuous reference plane for any inner signal layer.

In the 8 layer example, having one continuous plane and one discontinuous plane will not have much effect on the signal paths on S2. The minor effects on trace impedance would be immeasurable in the real world. You would need to watch that adequate bypassing is done for the power supplies. Those bypass capacitors become the conduit for return current across the splits.

thanx again.

i think i will stay at 6 layers.
the most critical is the memory bus, but the only split in it, is the Vmem_cpu and the Vmem_dimm, and i can connect them with few stitching-caps.

Its a stripline concept.

Provide the Solid plane reference for DDR signals because DDR trasnfering 2 data signals for single clock cycle.

Your trace impedence would be defined by the closest of referece plane which is 200um away (GND Plane) from your critical signals. For 60ohm traces you may get 3-4 mil of trace width.

it is stripline.