atferrari
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DISREGARD THIS POST. PROBLEM SOLVED
Micro 18F452 - Working in assembler.
I plan to derive timing for two simultaneous processes using:
a) CCP1 in compare mode against TMR1 that generates a clock which should exhibit NO jitter due to TMR0 interrupt occurrence (see below). This clock has no 50% duty cycle so CCPR1L and CCPR1H should be alternatively loaded with different values.
b) TMR0 (16-bit mode) overflow interrupt to get a time base, of namely 5 ms. Interference from interrupt in a) is acceptable since the time base is used in debouncing, LEDs and display routines but no clocks.
My questions:
1 - What is the best way to ensure that CCP1 compare interrupt is always served on the spot, with priority over TMR0 interrupt?
a) Making it "high" priority and TMR0 "low" priority, or both with same priority but checking the CCPI interrupt first in a sole ISR servicing them?
Seen reccomended quite often to stay away of priorities if at all possible but never a reason was given!!
2 - For "reloading" the value of TMR0 I've seen reccomended "adding" a value to current one in TMR0 registers insted of "loading" one, every time the ISR takes charge to start the new counting period.
Besides that "loading" instead of "adding" affects the prescaler if assigned, is it any other reason to consider? Found that told, many times in the Microchip forum but never actually explained.
Thanks for any help.
Micro 18F452 - Working in assembler.
I plan to derive timing for two simultaneous processes using:
a) CCP1 in compare mode against TMR1 that generates a clock which should exhibit NO jitter due to TMR0 interrupt occurrence (see below). This clock has no 50% duty cycle so CCPR1L and CCPR1H should be alternatively loaded with different values.
b) TMR0 (16-bit mode) overflow interrupt to get a time base, of namely 5 ms. Interference from interrupt in a) is acceptable since the time base is used in debouncing, LEDs and display routines but no clocks.
My questions:
1 - What is the best way to ensure that CCP1 compare interrupt is always served on the spot, with priority over TMR0 interrupt?
a) Making it "high" priority and TMR0 "low" priority, or both with same priority but checking the CCPI interrupt first in a sole ISR servicing them?
Seen reccomended quite often to stay away of priorities if at all possible but never a reason was given!!
2 - For "reloading" the value of TMR0 I've seen reccomended "adding" a value to current one in TMR0 registers insted of "loading" one, every time the ISR takes charge to start the new counting period.
Besides that "loading" instead of "adding" affects the prescaler if assigned, is it any other reason to consider? Found that told, many times in the Microchip forum but never actually explained.
Thanks for any help.
