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XOR, D-flip flop and MUX circuit for a phase detector - HELP

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Crusader370

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Hi All,

I am working on this project where I need to simulate the following circuits:

> Figure 4.4 shows an xor gate. I need to know how it works and the different parameters I would need for its functioning (which are Iss, Vb I1 and R1)
> Figure 4.5 shows a current-steering differential latch. I need to know what Vsource (biasing voltage should be)
> Figure 4.6 shows a current steering multiplexer I need know what Vsource (biasing voltage should be)

I really have no idea how these circuits work, and I need to understand them if I am going to simulate them. Any insight into their operation will be greatly appreciated, as I am really stuck.

Thanks a lot,

Crusader

https://obrazki.elektroda.pl/20_1175574099.jpg
 

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