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Native testbench and System Verilog

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ankit12345

ankit12345

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What is native testbench?????

How to use it????

What about Systemverilog????Is it better to use NVTB for SV????
 

**NATIVE TESTBENCH**

What about functional covarage using vcs????In system verilog.
assertion coverage --vcs supports.
Is this enough for functional coverage????

Added after 28 minutes:

whats the diff b/w sequence coverage and property coverage???
 

Re: **NATIVE TESTBENCH**

ankit12345 said:
What is native testbench?????
Click to expand...
It is Synopsys's Buzz word to denote thier "native compiled testbench (NTB), assertion and coverage" technologies. When it was started (guess 4 years back), SV was not around, so they supported OpenVera language and NTB was used as another "tool" instead of stand alone Vera tool. Vera as a tool can work with multiple simulators (NC, MTI, VCS), whereas NTB can only be used with VCS AFAIK.

Once SV became popualr they supported SV front end to the same engine and it is their SVTB solution now. So in a sense Synopsys has 2 TB solutions now:

Vera (stand alone)
NTB - with OpenVera language
NTB - with SV support

How to use it????
Click to expand...

Look in $VCS_HOME/doc/examples/nativetestbench/openvera/

What about Systemverilog????Is it better to use NVTB for SV????
Click to expand...

Well if you have legacy Vera code, use NTB and all new code write in SVTB. That's my suggestion.

BTW - do a google search for NTB synopsys, there should be several hits.

HTH
Ajeetha, CVC
www.noveldv.com
 

**NATIVE TESTBENCH**

Waiting for the answer.........

What about functional covarage using vcs????In system verilog.
assertion coverage --vcs supports.
Is this enough for functional coverage????

whats the diff b/w sequence coverage and property coverage???

THANKS IN ADVANCE
 

**NATIVE TESTBENCH**

In sv

Im implimenting verification using modules,not progam........
Its not full sv env.Its a mixture of sv and v.

I have class in one module and I want to creat objects in other module.

How to do that????
can hirarchial path supports????

any other solution???
 

Re: **NATIVE TESTBENCH**

ankit12345 said:
In sv

Im implimenting verification using modules,not progam........
Its not full sv env.Its a mixture of sv and v.

I have class in one module and I want to creat objects in other module.

How to do that????
can hirarchial path supports????

any other solution???
Click to expand...

Why would you do that? Why not declare class in a package and import where needed? Ankit - if you don't mind me saying this - you seem to be learning SV at a good pace but unfortunately without proper guidance. Given the magnitude of new constructs in SV you are more likely to use them in a wrong way and convince the management that it is not worth it! So please look at a good methodology for SV - say AVM, VMM, Truss etc. We at CVC specialize in all these areas.

Regards
Ajeetha, CVC
www.noveldv.com
 

**SYSTEM VERILOG**

Declared event in SV top module.

Im trying to use it in progam.

Can I????

Thanks in ADVANCE

Added after 1 hours 6 minutes:

In sequencess.....why events are not used????
 

Re: **SYSTEM VERILOG**

ankit12345 said:
Declared event in SV top module.

Im trying to use it in progam.

Can I????
Click to expand...

You can - it should work. Try posting full code for better help.
In sequencess.....why events are not used????
Click to expand...

B'cos sequences are built of boolean layer/expressions. Show us exact code of what you need.

Regards
Ajeetha, CVC
www.noveldv.com
 

**SYSTEM VERILOG**

Circular dempendence is still persist in specman while importing files.
Solution is creating a header file.

Weather this exists in SV????
Is it tool dependent???r Laungauge dependent????
 

Re: **SYSTEM VERILOG** vs NTB?

Ajeetha:

You mentioned "Native Test Bench" (NTB)

Forgive me for asking a 2nd time, but is this a Synopsys designed methodology? Or is it just a marketing buzzword to describe Synopsys's advanced simulator architecture? (I.e., the fact that it was native-compiled and executed on the host-machine at full-speed, unlike "emulated" programs which suffer through overhead of the PLI/VPI interface.)

I'm just trying to get a perspective of what we have today (IEEE Systemverilog 1800-2005) versus what was offered 3-4 years ago...
 

Re: **SYSTEM VERILOG** vs NTB?

Hi,

modelsim62c said:
Ajeetha:

You mentioned "Native Test Bench" (NTB)

Forgive me for asking a 2nd time, but is this a Synopsys designed methodology?
Click to expand...

It is not a methodology, rather a technology (SW).

Or is it just a marketing buzzword to describe Synopsys's advanced simulator architecture? (I.e., the fact that it was native-compiled and executed on the host-machine at full-speed, unlike "emulated" programs which suffer through overhead of the PLI/VPI interface.)
Click to expand...

Yes, this is what I would think NTB means.

I'm just trying to get a perspective of what we have today (IEEE Systemverilog 1800-2005) versus what was offered 3-4 years ago...
Click to expand...

Good idea, but I'm not sure why NTB is needed to understand that.

If you are based in Bangalore we can meet and I can share my perspective on this.

Regards
Ajeetha, CVC
www.noveldv.com
 

**SYSTEM VERILOG**

you can see the VMM
 

**SYSTEM VERILOG**

I think it would be easier to start with some examples. From this point of view, AVM from MentorGraphics will be more helpful for a beginner of SV.
 

**SYSTEM VERILOG**

Can anybody suggest me the good book for system verilog for verification.. I am the begainer.So i want to start with basics of system verilog...
 

Re: **SYSTEM VERILOG**

sujittikekar1 said:
Can anybody suggest me the good book for system verilog for verification.. I am the begainer.So i want to start with basics of system verilog...
Click to expand...

As we speak, we started a 10-day training on "Verificaion using SystemVerilog" based in Bangalore. Drop me an email ajeetha <> gmail.com if interested to join in!

Regards
Ajeetha, CVC
www.noveldv.com
 


**SYSTEM VERILOG**

Yes, this book is a good entry.
 

Re: **SYSTEM VERILOG**

Who can compare System C and System Verilog?
which is better for testbench?
ankit12345 said:
What is native testbench?????

How to use it????

What about Systemverilog????Is it better to use NVTB for SV????
Click to expand...
 

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