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VHDL==> Verilog (want to learn verilog, presently used vh

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s3034585

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Hi guys
can any one tell me how different is verilog from vhdl. i have been using vhdl for quiet a while and now i want to learn verilog. are they totaly diff or my vhdl understanding will be helpfull to learn....

let me know ur opinions on it..

thanks
tama
 

Re: VHDL==> Verilog (want to learn verilog, presently use

Hi,
It is easy to learn verilog when u r familiar with VHDL, The only diff b/w them is the way both or compiled.
 

Re: VHDL==> Verilog (want to learn verilog, presently use

Hi satyakumar
thnx for ur reply... i couldnt get what do you mean by the both way they are compiled. i mean wht is the diff here.. can u explain a bit...

thanks
tama
 

Re: VHDL==> Verilog (want to learn verilog, presently use

Hi dude

Actually , if u knwo VHDL , u can learn Verilog but thru a bit struggle .....Forget the coding part....Except the syntax..they would be the same almost...
But one thing what I had observed is that , it is difficult to synthesize a verilog code which is written in beavioural mode ...while it is easier in vhdl
 

Re: VHDL==> Verilog (want to learn verilog, presently use

VHDL is very typed language.... whereas verilog is based on C....
if you know C than its really much more easier than VHDL... to learn
 

Re: VHDL==> Verilog (want to learn verilog, presently use

pick up two books, one for VHDL and one for Verilog you will find the different. Look like you ask the question what's the different between English and French
 

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