Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[DC] Determine parameter in set_input_delay?

Status
Not open for further replies.
D

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
Hi all,

When use set_input_delay/set_output_delay, how to determine the -max/-min parameter? Is it calculated by hand , calculated by tools, or give out by some standard specification?

Code: 
set_input_delay -max 498  -clock EXTSCL [find port ddc_sda_i]
set_input_delay -min 0    -clock EXTSCL [find port ddc_sda_i]

set_output_delay -max 498 -clock CLK1MHZ [find port ddc_sda_o]
set_output_delay -min 0   -clock CLK1MHZ [find port ddc_sda_o]

Best regards,
Davy
 

General concept is to use time budgeting. 40% of clock period is used as input and output delays
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Hi Megastar007,

Thanks, so the delay is calculated by hand, is it right?

Best regards,
Davy
 

Hi ,

This should be as a part of specification .
In general if you are doing synthesis of module you do 40% of clk . But if you constrain the same at SOC you need to go through data sheet and get the same .


Thanks & Regards
yln
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
I think we should estimate the outside environment for the chip to give the input delay value. I am right?
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
If u synthesize modules which is nothing without outer environment, that use 40% clock period; if else, should refer datasheet of outer chip.
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Hi davyzhu,

It is totally dependent on the environment where your design is going to sit.

For example if your input is driven by a block/chip which is fast enough to give the output in 20% time
then your design budget is 80% of clock period.

For a block level or IP design these margins are specified by the architect whereas at chip level this
is driven by a application requirements.:|
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
these come under timing exception !! .....
which specifies delays on various ports
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top