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Clock gating of the registers banks in a design

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vahid_roostaie

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I want to gate the clock of the register banks of my design. as you may know there is an option named:sequential_cell in the set_clock_gating_style command. i don't want to use "latch" as sequential cell, but because some of the top level inputs of the design influence on so many register banks enable signals so DC couldn't insert clock gatinf logic for them and issues the following response : "combinational path from input port to FF. how can I insert clock gating without using latch as sequential cell?

is there any way to make DC to ignore the impact of the top level inputs on constructing the enable signal of the register banks?

FYI: my top level inputs have low transition and just selects mode of operation of the chip.
 

clock gating

Interesting. Why can't you use an AND gate to control the clock signal to a module or register?
 

Re: clock gating

I have seen so many designs with and or nand used as gating cell. what is exact warning/error you see?
 

clock gating

There should not be any problem!. Can you please lint ur design properly before synthesis
Sumit
 

clock gating

You can certainly use AND gates rather than integrated clock gating latches but the clock gating setup/hold timing from the flop that launches the enable signal to the AND gate need to be met, and this needs to be explicitely checked in timing. If you use an integrated clock gating cell, that particular timing arc is met by design.
 

Re: clock gating

vahid_roostaie said:
how can I insert clock gating without using latch as sequential cell?
Click to expand...

Inserting clock gating without latch, use command like below:
set_clock_gating_style -sequential_cell none

vahid_roostaie said:
is there any way to make DC to ignore the impact of the top level inputs on constructing the enable signal of the register banks?
Click to expand...

No. Power compiler ignore the enable signal generated from inputs.


quan228228
 

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