about clock skew - how to do data delay?

about clock skew

in my design , clock skew > data delay in many path,how can i do ?
my chip is altera's cyclon ,and soft is Quartus.

I THINK THAT U WILL HAVE TO DEAL WITH THE ROUTING THINGS. CHECK THE INTERNAL DESIGN AND TRY TO RE-ROUTE THE CIRCUIT. ELSE U CAN IMPLEMENT ASYCHRONOUS DESIGN

Hello Caecar,
According to my knowledge, you must be getting this error im timing analysis phase. Are you using any derived clocks in your design? Or are you using any PLL's in Cyclone?
This problem is a typical design problem if you are using a derived clock.
I have faced this kind of scenarios with my own designs which; in simulation work fine. Even in sythesis they look pretty, but when it comes to Timing Analysis in Quartus it spits out this error.
Please tell me if you are using two different clocks. If not please explain briefly about the design; I can help you in better way in that case.
For your reference I am giving you some guidelines:
1) This link is from altera support / solutions database. Please give it a look:
https://www.altera.com/support/kdb/rd07061999_3436.html
2) Please search for Application Note 123 "Using Timing Analysis in
the Quartus II Software". Refer to Page 17 in that document. It is >> Advance Timing Analysis > clock skew.
Please tell me if you can't download the application note. I will send you.
I hope it sloves your problem.

Thank your good and fast repliy!
In my design,there's 1 system clock,and it was div 3 clock signal.then skew was done.
20.48M(system clock) div=>2.048 div=>512k
=>64k

reclock

One trick I have used in board level designs to keep all levels of the division in phase is to use a D flip flop to reclock the final outputs using the highest frequency clock. This still makes a delay between the highest and the rest of the clocks. This is easier to fix with a delay or by starting with twice the frequency and dividing that down by 2 and reclocking.

I have never worked with @ltera's cyclon but if is similar to X!l!nx I guess you'll have DLLs or a similar de-skewer module, right? Or you don't get such things in cyclon? (snake_eyes mentions PLLs)

If they are available using them should reduce the skew a lot and you can also use it to divide your clock.

Do you have IBUFG or similar in cyclon?

-maestor

Convert your gate clock to clock enable.
I have do so in many case.