Sequence detector using state machines

hi all
i want to know sequence detector using state matchines

and i want information abt state matchines

Re: sequence detector

Here the code for a 11010 Sequence

------------------------------------------------------------------------------------------
module seqdet_11010(clk,reset,in,out);

input clk,reset,in;
output out;

reg out;

parameter st0 = 3'b000,
st1 = 3'b001,
st2 = 3'b010,
st3 = 3'b011,
st4 = 3'b100;
reg [2:0]currentstate,nextstate;


always @ (in or currentstate)
begin : comb

case(currentstate)

st0 : if(in == 1'b0)
begin
nextstate <= st0;
out <= 1'b0;
end

else
begin
nextstate <= st1;
out <= 1'b0;
end

st1 : if(in == 1'b0)
begin
nextstate <= st0;
out <= 1'b0;
end

else
begin
nextstate <= st2;
out <= 1'b0;
end


st2 : if(in == 1'b0)
begin
nextstate <= st3;
out <= 1'b0;
end

else
begin
nextstate <= st2;
out <= 1'b0;
end

st3 : if(in == 1'b0)
begin
nextstate <= st0;
out <= 1'b0;
end

else
begin
nextstate <= st4;
out <= 1'b0;
end

st4 : if(in == 1'b0)
begin
nextstate <= st0;
out <= 1'b1;
end

else
begin
nextstate <= st2;
out <= 1'b0;
end


default : begin
out <= 1'b0;
nextstate <= st0;
end

endcase

end


always @ (posedge clk or posedge reset)

begin : seq
if(reset == 1'b1)
begin
currentstate <= st0;
end

else
currentstate <= nextstate;
end

endmodule


---------------------------------------------------------------------------------------------

`include "seqdet.v"

module seq_det_tb();

reg clk;
reg reset;
reg in;
wire out;

seqdet_11010 u1(clk,reset,in,out);

initial

clk = 1'b1;
always
#5 clk = ~clk;

initial
begin
reset = 1'b0;
#10 reset = 1'b1;
#10 reset = 1'b0;
end

initial
begin
in = 1'b1;
#40 in = 1'b1;
#10 in = 1'b0;
#10 in = 1'b1;
#10 in = 1'b0;
end

initial
begin
$dumpvars();
$dumpfile("seqdet.vcd");
#200 $finish;
end

endmodule


-----------------------------------------------------------------------------------------------



Good luck

Re: sequence detector

Hi .if u want to write it in VHDL the code for 1010 sequence detector could be as shown.


library ieee;
use ieee.std_LOGIC_1164.all;
entity seq_detect is
port(x,clk:in std_logic;
zut std_logic);
end seq_detect;
architecture beh of seq_detect is
type state is(reset,g0,g1,g2);
signal current:state:=reset;
begin
process(clk)
begin
if(clk='1' and clk'EVENT)then
case current is
when reset =>
if x='0'then
current<=reset;
else
current<=g0;
end if;
when g0 =>
if x='1' then
current<=g1;
else
current<=g0;
end if;
when g1 =>
if x='1' then
current<=g2;
else
current<=g1;
end if;
when g2 =>
if x='1' then
current<=reset;
else
current<=g2;
end if;
end case;
end if;
end process;
z<='1' when current=g2 else '0';
end beh;