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What is a clock gating error?

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what is clock gating error?
what is the significance of AND gate in clock gating?
 

Re: about clock gating

being in education my first response is DO YOUR OWN Homework, but at the same time i like helping people, gating error is caused by gate pulses being delayed through a network
 

Re: about clock gating

because of and gata in clock gating there may chances of gliches in clock which is finally fed to flip flop
 

about clock gating

clock gating is helpful in power reduction
 

Re: about clock gating

hey
Clock gating is one way of providing control signal in a sequential system.
For example, if we want a flip flop to work only at certain timing instant then clock going through it can be and gated with a control signal which will go high only in that timing interval.
having said that, clock gating is a bad idea to use (for several reasons like delay introduced by and gate which lead to synchronization problems).There are more elegant ways to provide control signals.For example, in a D-flop and the input signal(the D signal) with the control signal and let clock come to it ungated.
Hope I'm making myself clear.Please Refer to a text on Digital Design for more details.


Regards
tronix
 

Re: about clock gating

I agree with tronix. Clock gating is a method of controling Flip Flops through their clock terminals. Althogh simple, Clock gating is not advisable since it makes the synchronous circuit partially asynchronous.
 

Re: about clock gating

The Joy of Electronics said:
I agree with tronix. Clock gating is a method of controling Flip Flops through their clock terminals. Althogh simple, Clock gating is not advisable since it makes the synchronous circuit partially asynchronous.
Click to expand...

1st off, clock gating SEEMS simple, but it is not. Because of side effect complex issues - such as Tighter Clock Tree Skew Control, DFT, and STA. But prudent work will overcome all these issues.

2nd - "Clock gating is not advisable" - that was true several years ago.
This isn't the case anymore with Modern ASIC/VLSI design, were Power savings is very crucial.
Clock Gating is today a common prefered practice for Power saving.
 

Re: about clock gating

refer some Digtal integrated books
 

Re: about clock gating

An AND Gate is required in clock gating because u need to allow the clock only when ur gating control signal is ON.....
 

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