Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Req. clarification about the managing of the ram in ISE 52

Status
Not open for further replies.
gnomix

gnomix

Member level 4
Joined
Jun 14, 2001
Messages
75
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
italy
Activity points
649
Hi to all,
I have the following question about xilinx design flow:
I have compiled my design that contain an initialized ram memory,
for debug I need to modify the value stored into this memory and the only way that I know
is to manage it into the coregen and then re-compile all the project.
The time to perform this flow is about 3 hour (Sigh).
I asked to our distributor (Xilinx certified FAE) a solution but I haven't received a valid answer.
Can someone help me to understand how I can change the initialization memory contents without re-compile all the project?

Regards Gnomix
 

What do you mean when you say "recompiling the whole project"?

Do you mean compilation, synthesis and PAR?

The easiest whay to do it is to initialise your RAM in the UCF file, this involves doing the translate, map and par again but that is what you get, at least you dont have to re-synthesize it.

One very smart way of doing it would be using FPGA Editor and modify the INIT value for your RAM in the editor, that shouldn't take more than 5 minutes nut I am not sure if FPGA Editor supports editing INIT values for RAM.

Maestor
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top