moloned
Newbie level 3
Having installed Xilinx ISE 5.2i I am seeing about a 10% increase in delay for a HW multiplier based design on a 4k -6 speed grade device which also includes a number of long adders (70-bit), compared to 5.1i.
Has anybody else seen similar problems?
The main difference I can see using the speedprint utility is the 5.2i release has PRODUCTION data from lot # 1.114 Dec/02 as opposed to ADVANCE data from lot # 1.110 Jul/02.
My difficulty is interpreting the data for multipliers and such in the reports generated by speedprint. I can't seem to find corresponding timing diagrams annotated with the same labels in the Xilinx documentation.
Do you have any idea where I can find this info.?
Has anybody else seen similar problems?
The main difference I can see using the speedprint utility is the 5.2i release has PRODUCTION data from lot # 1.114 Dec/02 as opposed to ADVANCE data from lot # 1.110 Jul/02.
My difficulty is interpreting the data for multipliers and such in the reports generated by speedprint. I can't seem to find corresponding timing diagrams annotated with the same labels in the Xilinx documentation.
Do you have any idea where I can find this info.?
