Why PMOS for pull up and NMOS for pull down?

Hi all,

I am still confusing why we always learn in Uni that source of nMOS need to tie to GND and source of pMOS need to tie to VDD.

I only can figure out that if souce of nMOS is tie to VDD will cause Vout = VDD-Vth, and contrastly if souce of pMOS is tie to VDD will cause Vout = Vth. But why this happen?

Please add in additional information when necessary.


Thanks!

Hi
source of nmos can't connect to vdd because
after connection its name is drain.
current flow from vdd to other node and can't flow against of nmos current.
I hope that it will be useful.
regards

Don't confuse , i can give the exact answer,

as u said , when nmos and pmos are interchanged in the basic cmos inverter , the output swing will be from vdd-vth to vth.

reason: take nmos pass transistor , u give 1 terminal to vdd and the gate terminal (vgs) to vdd. now u can't get vdd at the other(sourse) terminal of nmos , this is bcoz when the sourse is charged to vdd-vth then the effective vgs = (vdd-(vdd-vt)) => vgs = vt. now u can't furthur charge the sourse as it goes into the cutoff if the voltage is less than vt for the nmos transistor. so nmos transistor is off(cutoff) and the output is vdd-vt.

apply the same for pmos , now analyse the cmos inverter gate , u will find the answer.

i'll try to explain it
when the input to the NMos is low(0) this means Vgs less than Vth so the NMOs is off
For The PMOS when input=0 so Vsg>|VTp|(which is negative) so the transistor is on and o/p =VDD so PMOS called pull up

for i/p is high the reverse 'll happen

Hi,

PMOS transfer good value of 1 and NMOS transfer good value 0
(means you can get rail to rail swing)

Say you have your Vdd connected to the drain of the nmos and the output is taken at the source. When apply Vdd to the input terminal and if the gate-source voltage Vgs > vth, then you have an inverted channel and Vds > 0 causes current to flow to the source charging it up and pulling the source voltage up. The source voltage cannot go above Vdd-vth because when the source voltage reaches this limit there is no channel for current to flow from drain to source, and hence the source voltage cannot increase.

Someone correct me if this is not right.

mathi said:

Say you have your Vdd connected to the drain of the nmos and the output is taken at the source. When apply Vdd to the input terminal and if the gate-source voltage Vgs > vth, then you have an inverted channel and Vds > 0 causes current to flow to the source charging it up and pulling the source voltage up. The source voltage cannot go above Vdd-vth because when the source voltage reaches this limit there is no channel for current to flow from drain to source, and hence the source voltage cannot increase.

Someone correct me if this is not right.

Click to expand...

If you connect source of NMOS to VDD, the new name of source is drain.
because in MOSFETs there is no difference between drain and source and potential difference seperate them.
regards

Hi all,
I will try to answer, if not corect feel free to coment.
In NMOS source and drain is doped with n-type material and substrate is of p-type, the biasing would be drain to VDD, source to GND and gate Vin. The substrate is conected to GND, to make the NMOS conduct the Vin>vt. But Vt depends on body bias, mobility and doping concentration as well as channel length.
If body is conected to GND then the potential diferenc b/w source and body is zero, hence with applied Vin the channel region get inverted without body effect(since there is no vbs). As the body voltage increases there is increase in vbs and hence Vin needs extra effort to overcome the Vbs and to make the channel invert by sourceing electrons from source. the same explaination holds for PMOS wrt holes.

Thank you for the replies.

I had got the idea behind that.

cheers!....

I also try to learn it.
many thanks,
cheelgo