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How to simulate a bidirectional port in VHDL?

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alexz

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How can I simulate a bidir (inout) bus in VHDL?
It does not seam to be working when I simulate it normal way.
 

Re: Bidirectional port

What exactly is not working? You must tristate the signal when you want to read it (should work as output) by applying a 'Z' and apply what you want when is supposed to be an input. Of course, you probably have a signal to control the direction (in or out).
 

Bidirectional port

in your test bench file should be something like that


driver_signal <= value when < condition > else (others => 'Z');
 

Re: Bidirectional port

Iouri said:
in your test bench file should be something like that


driver_signal <= value when < condition > else (others => 'Z');
Click to expand...

That is just a tristate buffer isn't it?
I am using this for the OUT direction. And just reading from the bus directly for the IN direction
 

Bidirectional port

yes this is tri-state buffer
 

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