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High impedence state for output

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chang830

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Hi,
In some circuit/product, there is a spec of high output impedence for the output when in the disable or shutdown state. I wonder what it is exactly mean? Why we neet it? And how we implement it in the design?

Thanks
 

the transistors in the path from supply to ground are all off when the disable state.
 

**broken link removed**

**broken link removed**

Regards,
IanP
 

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    chang830

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You're probably talking about a tri-state output circuit. Take for instance the example attached. If a=0 and b=0 you would have Vout≈Vcc (cause M1 would be cutoff and M2 would be on triode region) which corresponds to a logic 1. If a=Vcc and b=Vcc Vout≈0 (cause M2 would be cutoff and M1 would be on triode region) which corresponds to a logic 0. If a=0 and b=Vcc both M1 and M2 would be on triode region so Vout≈Vcc/2. There would be a very small resistance value between Vcc and GND (almost shorcut) so try avoiding this. NOW!! if a=Vcc and b=0 both M1 and M2 are on cutoff region so the impedance value you get from your output into your circuit would be VERY VERY high.

This is used on circuits which share the same output (Vout) to avoid load effects. Try to think that the attached circuit is the output stage of a memory which shares the same bus with an ADC to comunicate with a processor. If the ADC what's to "talk" to the procesor, the memory should not be trying to talk at the same time cause shortcuts could occur, so the memory is on HIGH IMPEDANCE state during the time the ADC is expressing itself.

Hope I made myself clear,

diemilio.
 

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    chang830

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diemilio said:
You're probably talking about a tri-state output circuit. Take for instance the example attached. If a=0 and b=0 you would have Vout≈Vcc (cause M1 would be cutoff and M2 would be on triode region) which corresponds to a logic 1. If a=Vcc and b=Vcc Vout≈0 (cause M2 would be cutoff and M1 would be on triode region) which corresponds to a logic 0. If a=0 and b=Vcc both M1 and M2 would be on triode region so Vout≈Vcc/2. There would be a very small resistance value between Vcc and GND (almost shorcut) so try avoiding this. NOW!! if a=Vcc and b=0 both M1 and M2 are on cutoff region so the impedance value you get from your output into your circuit would be VERY VERY high.

This is used on circuits which share the same output (Vout) to avoid load effects. Try to think that the attached circuit is the output stage of a memory which shares the same bus with an ADC to comunicate with a processor. If the ADC what's to "talk" to the procesor, the memory should not be trying to talk at the same time cause shortcuts could occur, so the memory is on HIGH IMPEDANCE state during the time the ADC is expressing itself.

Hope I made myself clear,

diemilio.
Click to expand...

Hi diemilio,
Your explanition is very great!!! It is very helpful to me. Thanks a lot.
 

I have a question now.
If it's the output stage of a memory, there will be pull-up resistor,right? then it's not high impedance.
 

renwl said:
I have a question now.
If it's the output stage of a memory, there will be pull-up resistor,right? then it's not high impedance.
Click to expand...

Not necesarily. I've worked with memories with three state output stages... like the HM6116 which has an "output enable" input that when is high, all your outputs are on tristate mode, and when is low all your outputs work normally.

There are some memories with "open collector" or "open drain" outputs (which work with the pull-up resistor that you mentioned)

Here you can find the diference between those two output stages...

https://zone.ni.com/devzone/cda/tut/p/id/3544#toc1

diemilio

Added after 3 minutes:

chang830 said:
Hi diemilio,
Your explanition is very great!!! It is very helpful to me. Thanks a lot.
Click to expand...

I glad it helped you... :D
 

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