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How to implement DFT with single scan clock

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newcpu

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Hi all,
I am work on DFT for a design with three clock domains. Could anyone tell me how to implement DFT with singe scan clock? Do I need to add mux to bypass the clocks of the other two clock domains? And drive clock pins of all the registers with the single scan clock?
Thanks a lot.

Best Regards,
Bangtian Jia
 

Hi newcpu,
The answer is yes. The muxs must be added for selection of scan clock when the chip is in SCAN_MODE test.

Sincerely,
Jarod
 

You don't need to worry about it. The DFT will ignore different clock, it will connect all sequential cell automatically.
 

what is the common things that we can observe in both RTL and gate netlist?(Sequential circuit)
 

tmanoz said:
what is the common things that we can observe in both RTL and gate netlist?(Sequential circuit)
Click to expand...

you mean the waveform response?
if yes, then what in common is flip-flop latched data will be the same with no timing violation.
 

netlist is better regarding timing point of view.
 

If you use Synopsys tools you can mix scan chains from different clock assuming that in test mode all clock network use the same clock.

set_scan_configuration -clock_mixing ...
 

Use a dedicated clock for test process. This can be done by a mux
 

hawk_chenbo said:
You don't need to worry about it. The DFT will ignore different clock, it will connect all sequential cell automatically.
Click to expand...

Of coure, the MUX inserting for clock selection must be done.
But many timing problem must be considered, when you just use one only clock.
 

If you will use a single clock to scan all regs, you must add some Muxs, but if you only insert all SDFF to all chains, you dont need to add Muxs!

Added after 6 minutes:

I am a DFT engineer, we may discuss some questions about DFT.
 

Hi ,
Eventhough you convert all DFF -> SDFF of all chains ,if there are multiple clock domain flops in a chain ,then to handle this clock muxing is done .Also if the paritcular clock is not handled from the top level & its generated internally .Then test_clk has to be muxed with func clock.

Regards
Chandhramohan
 

When mucking around with the clocks in multi-clock domain chips you are likely to have timing problems. If you rebalance the clock tree so that one clock pin can drive all FFs in test mode you will effect performance in functional mode. I suggest that you give each clock domain it's own clock pin for test mode. That will have the least impact on your clock tree.
 

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