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Interview Question --- Design a black box...

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jayanth03

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Design a black box whose input clock and output relationship as shown in attachment.
I think I know how do do it using HDL...

In Verilog: Output = repeat (2) @ (posedge clk) clk

Can some one please tell me how to design this using logic gates and FF's.

Thanks
Jayanth
 

This is the way!

Code: 
        +------------+
        |            |
        |  +-----+   |
        +--|D   Q|---|---+
           |     |   |   |       _____
           |     |   |   +------|     \
 CLK       |     |   |          |      )---- OUT
 ----+-----|>  /Q|---+   +------|_____/
     |     +-----+       |
     |                   |
     |   +------------+--+
     |   |            |
     |   |  +-----+   |
     |   +--|D   Q|   |    
     |      |     |   |
     |      |     |   |
     |      |     |   |
     +-----o|>  /Q|---+
            +-----+
 
Give D input to D filp flop --> xor of clk and Q(OUT)
 

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