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Help me convert convert a 50 MHZ clock into 44.1 KHZ clock

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rsrinivas

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Hi
I need to convert a 50 MHZ clock into 44.1 KHZ clock.
A verilog synthesizable code to be put in an FPGA.
pls suggest.
if i use a register(10 bit)i can divide the clk into 48.8 KHZ.
 

clk divider

If you are using ISE, ten you can add a DCM (Digital Clock Manager) from the IP core generator

DCM have a clock synthesizer , you enter the input clock frequency and the desired output
 

Re: clk divider

That ratio is somewhat awkward, but you can do it in a Xilinx FPGA with two DCMs plus a simple divider. (Beware, cascading the CLKFX of two DCMs isn't a great idea because of compound jitter.) The DCM parameters may vary depending on which FPGA you are using.

This works with a Spartan-3 compiled with ISE 8.1.03i:
Code: 
module top (clk50M, clk44100);
  input             clk50M;
  wire              clkadcm, clka, locked;
  reg         [4:0] reset = 0;
  wire              clkb;
  reg         [9:0] count = 0;
  output reg        clk44100 = 0;

  // synthesize 50 MHz * 21/25 * 21/25 / 800 = 44100 Hz

  DCM dcm1 (.CLKIN(clk50M), .RST(1'b0), .CLKFX(clkadcm), .LOCKED(locked));
  defparam dcm1.CLK_FEEDBACK       = "NONE";
  defparam dcm1.CLKFX_MULTIPLY     = 21;
  defparam dcm1.CLKFX_DIVIDE       = 25;
  defparam dcm1.CLKIN_PERIOD       = 20.0;
  defparam dcm1.DFS_FREQUENCY_MODE = "LOW";

  BUFGMUX buf1 (.I0(clkadcm), .S(1'b0), .O(clka));

  always @ (posedge clka)
    reset <= {reset,locked};

  DCM dcm2 (.CLKIN(clka), .RST(~reset[4]), .CLKFX(clkb), .LOCKED());
  defparam dcm2.CLK_FEEDBACK       = "NONE";
  defparam dcm2.CLKFX_MULTIPLY     = 21;
  defparam dcm2.CLKFX_DIVIDE       = 25;
  defparam dcm2.CLKIN_PERIOD       = 23.8;
  defparam dcm2.DFS_FREQUENCY_MODE = "LOW";

  always @ (posedge clkb) begin
    count <= !count ? 799 : count - 1;
    clk44100 <= !count;
  end
endmodule
 

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    rsrinivas

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