design issue about CML/SCL level shift

scl cml

Hi, folks

I have a simple question about the design issue of CML/SCL, which is short for source coupled logic. Especially, I'm intrested in the stacked SCL circuits such as flip-flop or MUX.

For example, in the classical CML flip-flop based on bipolar transistors, the level shift for the clock signal is necessary to secure the transistors on the bottom level to operate in the right working region. As shown in the first picture below, the level shift function is implemented by the emitter follower at the left.

But for the source coupled logic flip-flop based on CMOS transistors, the level shift is rarely addressed by any reference. It seems that someone did use source follower to implement the level shift as in the bipolar process. Also someone just ignored it at all. It means data signal to top level transistors have the same common mode voltage as the clock signal to bottom level transistors. As shown in the second picture below, in/inb and clock/clockb have the low and high input voltage as Vdd-Vswing and Vdd.

So it really makes me confused at this point. What do you guys think about that? Any inputs will be appreciated much.

design issue about CML/SCL level shit

Hi, where are those IC gurus? Nobody can anwser this question?

Re: design issue about CML/SCL level shit

I think the bipolar is current driver circuit,if you directly use CLK driver the bias,
there are big current.But IF you use CMOS ,for its none gate current,so you can driver the bias .

The reason you need the level shift in the bipolar design is to keep Q5 & Q6 out of saturation. Without the level shift the potential on the base of Q5 & Q6 will be too high which will lead to forward biasing the collector-base junction (saturation) of these transistors. This will kill your beta, Ft, thus the ac performance of these transistors.

On the other hand, for mosfet devices, there is no bipolar saturation effect. Therefore, you don't need a level shift, but just make sure that these devices are operating in the mosfet saturation region. The higher potential on the gate increases the overdrive (Vt+Vgs) of these transistors thus increasing the transconductance/current drive of these devices. Therefore, you can use a smaller device, with smaller parasitic capacitances, to switch the clock signal. One thing you will have to make sure is that your Vt+Vgs is so large that it will increase your Vds_sat voltage. The increase in Vds_sat for these transistors will decrease the voltage headroom of your current source mosfets. If the headroom of the current source mosfet decreases below its Vds_sat then your current source transistors will be taken out of the mosfet saturation region.