Max++
Junior Member level 3
from code below
Library ieee;
Use ieee.Std_Logic_1164.All;
Entity lighting is
Port(datain:in Std_logic;
dataout
ut Std_Logic
);
End lighting;
Architecture RTL of lighting is
begin
process(datain)
begin
dataout <= datain;
end process;
end RTL;
The Simulate result show that dataout will delay from datain around 15 ns.
(Use MAX Plus ||)Is this the normally result of FPGA
and
Max Plus || have some option for ignore this delay because it difficult to look.
Library ieee;
Use ieee.Std_Logic_1164.All;
Entity lighting is
Port(datain:in Std_logic;
dataout
ut Std_Logic );
End lighting;
Architecture RTL of lighting is
begin
process(datain)
begin
dataout <= datain;
end process;
end RTL;
The Simulate result show that dataout will delay from datain around 15 ns.
(Use MAX Plus ||)Is this the normally result of FPGA
and
Max Plus || have some option for ignore this delay because it difficult to look.