question about access time of sram

I want to figure out how the port number of an sram give influence to the access time.for the following three kings of sram in asic
1)single port, write and read at different time
2)dual port, just two ports which each is like 1)
3)dual port, one for write and one for read
using the same foundary and similiar layout, if 1) gets an access time of 2 ns, what about 2) and 3)? Just generally speaking, thank you!

Hi..
I am not been able to understand your question quite clearly. I am replying in accordance to what I understood.

You want to know the impact on access time based in 3 different scenarios.

The slowest in terms of acess time will be case 2.
Next will come the case 3.
Single port memory will be fastest in them all.

In case you are interested in knowing why hen I will advise you to find material of dual port memcell, memcell used for FIFO design and single port memcell.
Dual port memcell is the slowest of all.
Then comes the FIFO memcell.
Single port memcell is the fastest.

Though it has been seen that sometimes case 3 can be faster than case 1. So, we cannot be really sure about case 1 and case 3. What I mentioned above is a general case.

I hope it helps.

Thank you very much nitu.You've given enough infomation to me.
I never heart about the kinds of memcell you mentioned.
Maybe I can find those materials in some books?
Is there any recommandations?
Thank you again.

I will not recommend any book as I do not know about any book on memories.

But you can search on IEEE to find Dual Port CMOS SRAM, FIFO SRAM.

2) is the same as 1)
But 3) is the slowest due to more loading at bit line.