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hi!! y nand gate preferd over and gate for layout

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avg_emp

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hi all!!
Why 'nand gate' is prefered over 'and gate' for design of transistor level in physical design layout.
Thanx!
 

remember tat an and gate is made from a nand gate and an inverter(total 6 cmos trans)
nand is an universal gate any logic can be built from it.
to make the whole thing uniform only one type of gat has to be used.(it's helpful for statistical purposes like finding area and no of gates).if u use a combination of different gates the calculations of delay may be affected because different type of gates have different delays.
 

Because of the inverting property of the transistor, the gate straight way obtained from transistors is either a NAND or NOR gate. To convert it into AND or OR gate we again need extra inverter.
Moreover, any boolean function can be implemented using all NAND gates.

So why not to use gates that take smaller area(less number of transistors) and less delay and yet implement all our functionalities:))
 

and agte is realized from nand gate followed by inverter.and u need 4 transistors for nand and 2 for inverter in CMOS design.so in total 6 devices and need more area and other disadv as more devices than nand alone.and all the realizations which r to be done using and gate can be realized using nand.
 

1. nand and nor gates are universal gates
2. gates in layout r realised using the CMOS logic which in itself is a inverter.
thus, with the simple CMOS logic we find that nand and nor gates which are inverted logic's use less number of gates as compared to 'and' and 'or' gates.
I hope this makes u clear.
 

Thanx!!!! a lot to all now & in future in advance for sorting the queries.
 

as nand gate has p type in parrallel where as nor has ptype in series so it occupy more space...
so nand is prefer
 

for the layout level, we can first get a NAND with 4 transistors(CMOS fab), and then we can get an AND gate by following an inverter with the NAND.
 

avg_emp said:
hi all!!
Why 'nand gate' is prefered over 'and gate' for design of transistor level in physical design layout.
Thanx!

First of NAND gate is Universal Gate.Any function can be design from that.For layout part it requires 4 transistors and for AND gate it required two more in which case area is more
 

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