gauz
Junior Member level 3
Hi,
I have a design, the rtl simulation is ok, and then
1, after synthesis(ise62), the gate(translate) simulation output data is ok, while
there are violations reported when runing simulation. I think it's reasonable
2, after map, the ise report hold time violation. when run simulation, the output
result is unknow(x). then I specify "+no_notifier" ,the result is ok. it's
reasonable too.
3, after p&r, the STA reports no timing violation, but when run simulation, still
report timing violation in "X_FF", and the result is still unknow(X), what's the
matter? I think there shouldn't be any violation any more with STA timing fixed.
could anyone help???
Thanks a million!
gauz
I have a design, the rtl simulation is ok, and then
1, after synthesis(ise62), the gate(translate) simulation output data is ok, while
there are violations reported when runing simulation. I think it's reasonable
2, after map, the ise report hold time violation. when run simulation, the output
result is unknow(x). then I specify "+no_notifier" ,the result is ok. it's
reasonable too.
3, after p&r, the STA reports no timing violation, but when run simulation, still
report timing violation in "X_FF", and the result is still unknow(X), what's the
matter? I think there shouldn't be any violation any more with STA timing fixed.
could anyone help???
Thanks a million!
gauz