Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can I restrict the expression input of case statement in VHDL?

Status
Not open for further replies.

lightofspace

Newbie level 5
Joined
Oct 18, 2006
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,355
Hello there!!
I have question about Case statement, can I restrict the expression input of case statement, to make it more clear I will review an example:

--------------------------------------------------------------------
ENTITY interface IS
PORT (input: IN std_logic_vector (15 downto 0));
-- the ports interface still in the construction phase
END ENTITY interface;

--
ARCHITECTURE behavioral OF interface IS
BEGIN
mapping: Process (input)
Begin
case input is
when "000000001" => writeline(output, "Clear Display");
when "000000011" => writeline(output, "Return Home");
when "000000010" => writeline(output, "Return Home");
when "000000001" => writeline(output, "Clear Display");
end case;
End Process;
END ARCHITECTURE behavioral;
--------------------------------------------------------------------
so that I want case not to take all the bits (from 0 to 15) in "input", I want just to make comparison on the first 8 bit like "case input (4 downto 11) is", is this possible in case statement of vhdl?

Thanks
ahmad
 

Re: case statement: VHDL

yoo can make internal signal or variable from part of your input


signal SignalName : Std_logic := 'U';

SignalName <= input (7 downto 0));


then :

case SignalName
 

case statement: VHDL

Why not synthesize and simulate your VHDL code in the Maxplus II or Xilinx ISE to see whether it works or not? I think this is a simple and good way to learn it. Then if you encounter any problems during the process of synthesis and simulation, you can post your questions here.
 

Re: case statement: VHDL

I think you can use others..if you want only the data which u mentioned to be seen..
for example..
case xxx is
when (others)=>"00000"
 

Re: case statement: VHDL

ENTITY interface IS
PORT (input: IN std_logic_vector (15 downto 0));
-- the ports interface still in the construction phase
END ENTITY interface;

--
ARCHITECTURE behavioral OF interface IS
BEGIN
mapping: Process (input)
Begin
case input is
when "000000001--------" => writeline(output, "Clear Display");
when "000000011--------" => writeline(output, "Return Home");
when "000000010--------" => writeline(output, "Return Home");
when "000000001--------" => writeline(output, "Clear Display");
end case;
End Process;
END ARCHITECTURE behavioral;



solution to your problem is that " - " in std_logic is for a don't care condition(VHDL).but be care ful while synthesis of this code as many synthesis tool think of it as redundant code and may not synthesis a ckt. as per your requirement
 

Re: case statement: VHDL

before using the signal directly for case..first make assignment to variable and then that variable you give for case statement

On synthesis..you will get only wire used and so you have selected only of your choice

Don't go for don't care (-)...bcoz depending upon the logic it will redunt it and so there will be vast difference in post synthesis simulation...
 

Re: case statement: VHDL

Hi,
Someone has rightly said to declare another variable for the required bits.
you can declare a variable of your desired range and assign it the concerned bits of input. then this variable can be used in case statement.

cheers:)
 

Re: case statement: VHDL

Tan said:
I think you can use others..if you want only the data which u mentioned to be seen..
for example..
case xxx is
when (others)=>"00000"
hi tan, i guess u were confused a bit
he wants to take just 8 bits from his input signal
not take some of the cases and leave others where u can use others:)

and for ahmad,
make a variable with the required dim of the input and use it in the expression of the case

ARCHITECTURE behavioral OF interface IS

BEGIN

mapping: Process (input)

variable tested_input: std_logic_vector(ur range);
Begin

case tested_input is
-------
-------
-------
end case;

End Process;
END ARCHITECTURE behavioral;


good luck,
Salma:)
 

Re: case statement: VHDL

convert the given 16bit binary input into octal value ,then convert the octal into 9bit binary value.then use the 9 bit binary as input in case statement...

Added after 16 minutes:

convert the given 16bit binary input into octal value ,then convert the octal into 9bit binary value.then use the 9 bit binary as input in case statement.while giving the 16 bit binary input..
 

Re: case statement: VHDL

Hello friend!, simple do this
-----------------
Signal sig : std_logic_vector(23 downto 0);

Case sig(15 downto 8) is
when "00000000" => .........
when "00000001" => .........
when "00000010" => .........
When others =>
End case
--------------------
This is synthesizable and beleive me, I have used this type of case statement for fine delay routines in case statement execution!......
 

Re: case statement: VHDL

In my opinion, you can just use an alias declaration, like this:

architecture Behavioral of apart is

signal term: std_logic_vector(15 downto 0);
alias for_case: std_logic_vector(7 downto 0) is term (11 downto 4);

begin
process (for_case)
begin
case for_case is
when x"00" => ...;
when x"01" => ...;
when x"02" => ...;
when others => ...;
end case;
end process;
...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top