Looking for ASIC FE Opportunities in USA/Canada/Europe

Hi all

I am looking for an opportunity in front-end ASIC Design/Verification in USA/Canada/Europe. Below is my brief profile:

� ASIC front end design/validation engineer, presently employed at Bangalore, India (1-2 years experience).
� Job responsibility involves front end validation for the PCI-express interface of next generation chipsets.
� Holds a Masters Degree in Microelctronics & VLSI Design from Dept. of Electronics & Electrical communications Engineering, Indian Institute of Technology, Kharagpur, India with CGPA 9.78 out of 10.
� Has got a total of eight publications in international/IEEE conferences in the VLSI/Image processing area.

I would highly appreciate if anybody becomes able to help me out in this regard.
Also, the senior guys, can you find some time to have a look at my resume and suggest changes/modifications required?

Thanking you in anticipation

Joydeep Bhattacharyya

masters in vlsi design in canada

Sorry, Donno why the file didn't upload properly.

Just pasting it here:


JOYDEEP BHATTACHARYYA

Email ID: joydeep.bh@gmail.com
joydeep_iitkgp@yahoo.co.in
Date of Birth: 28.12.1978
Contact no: +91-9343097160

PROFILE:
ASIC/VLSI front end design/validation engineer with 1-2 years of relevant experience. Flexible committed individual with strong communication skills looking for a challenging career opportunity in the field of chip design/verification.

SUMMARY:
• ASIC front end design/validation engineer , presently employed at Intel Corp, Bangalore, India.
• Job responsibility involves front end validation for the PCI-express interface of INTEL’s next generation mobile chipsets.
• Holds a Masters Degree in Microelctronics & VLSI Design from Dept. of Electronics & Electrical communications Engineering, Indian Institute of Technology, Kharagpur, India with CGPA 9.78 out of 10.
• Has got a total of eight publications in reputed international conferences in the relevant area.

EXPERIENCE:
• Since July 2005, part of Intel Corporation’s Mobility Chipset Front end group at Bangalore, India. Responsible for validation of the PCI express interface for Intel’s next generation mobile chipsets. Has got a good understanding upon PCI express protocol and its validation (tracker/checkers). Writes Chameleon (a hybrid PERL application) based tests to validate chipset features, finds RTL/Environment bugs and proposes/validates bug-fixes. Reviews testplans and bug-docs and writes tests to cover testplan holes.
• As a Junior Project Assistant in the R&D project “Design and development of a porous silicon based integrated smart pressure sensor“ ( sponsored by ISRO, Bangalore ) at I.I.T. Kharagpur,India ( May 2003 – May 2005 )

TECHNICAL EXPERTISE:

DESIGN TOOLS : Modelsim 7.0
HDL : Verilog
SOFTWARE SKILLS : C,C++., PERL
APPLICATION PACKAGES : MATLAB.
ASSEMBLY LANGUAGES : 8085.
EDUCATIONAL QUALIFICATION:

• M.S (Electronics & Electrical Communication Engg.) from IIT Kharagpur, Specialization: Microelectronics and VLSI Design, ( CGPA 9.46 out of 10), July 2005.
• B.E (Electronics & Telecommunication Engg.) from Jadavpur University, Kolkata with 81.2 % in 2001.
• Higher Secondary from West Bengal Council of Higher Secondary Education with 89.9 % in 1997 (8th position in state among nearly 4 lakhs students ).
• Secondary from West Bengal Board of Secondary Education with 91.2 % in 1995 (13th position in state among nearly 5 lakhs students).

PROJECT (M.S) :

TITLE: Design and Development of an Embedded Ultrasound Imaging System

DESCRIPTION:

• Setting up the system specification, Design and analysis of algorithms for different modules of an ultrasound system along with architectural design and FPGA implementation of a few modules
• Implementation of a real time noise cleaning algorithm to remove the speckle noise present in ultrasound echocardiographic images. The module works with 115 frames/second and consumes a total of 106,567 gates.
• Design of a CORDIC based real time scan conversion unit for ultrasound imaging and it’s implementation in Xilinx FPGA.The architecture is suitably pipelined and parallelized in order to increase the throughput of the system. Total number of gate count is 1, 50,186.
• Algorithm development and VLSI implementation of dynamic receive apodization unit for a digital delay-sum beamformer. The design is based on pipelined CORDIC, works with 40 frames/s and consumes a total of 22,586 gates.
• VLSI implementation of real time delay generation for a digital delay-sum beamformer. Corresponding delay memory has been designed utilizing the BlockRAMs available in the device.

PUBLICATIONS:

1. Real Time Noise Cleaning of Ultrasound Images, 17th IEEE Symposium on Computer-Based Medical Systems, Bethesda, Maryland, pp. 379-384, 24-25 June 2004. Co-author: A.Hazra and S. Banerjee.
2. Architectural Description of an Embedded Ultrasound Imaging System, International Conference on Biomedical Electronics & Telecommunications (BET-’04), Dec 9-10, 2004, Visakhapatnam, India, pp. 249-253. Co-author: A.Hazra, R.Mehta and S. Banerjee.
3. A CORDIC Based Real Time Scan Conversion Unit for Ultrasound Imaging, International Conference on Imaging, Beijing, China, May 23- 26, 2005. Co-author: Shayak Banerjee, Anindya hazra, Swapna Banerjee
4. Real Time Dynamic Receive Apodization for an Ultrasound Imaging System, 3rd International Conference on Computing, Communications and Control Technologies, July 24-27, 2005 - Austin, Texas, USA, Co-author: P.Mandal, R.Banerjee and S. Banerjee.
5. Design, Fabrication, Testing and Simulation of Porous Silicon Based Smart MEMS Pressure Sensor, 18th International Conference on VLSI Design and 4th International Conference on Embedded Systems, , Kolkata, India January 3-7, 2005. Co-author: C. Pramanik, T.Islam, H. Saha, S. Banerjee, S. Dey.
6. A Real Time Speckle Noise Cleaning Filter for Ultrasound Images, 19th IEEE Symposium on Computer-Based Medical Systems, Salt Lake City ,Utah,, June 22-23, 2006, Co-author. B. Mazumdar , A. Mediratta , S. Banerjee .
7. An Embedded System Design of Selective Window Speckle Noise Suppression Filter for Ultrasound Images , 1st International Conference on Industrial and Information Systems, Peradeniya , Srilanka, August 8-11, 2006. Co-author: B. Mazumdar , A. Mediratta , S. Banerjee .
8. Architectural Design and Implementation of a PC based Ultrasound Imaging System, 10th IEEE VLSI Design and Test Symposium, Goa, India, 9-12 August 2006, Co-author: B. Mazumdar , A. Mediratta , S. Banerjee.

REFERENCES:

Prof. Swapna Banerjee
Professor, E&ECE Dept.
IIT Kharagpur, Kharagpur, India.
E mail ID: swapna@ece.iitkgp.ernet.in


Dr. Anindya Sundhar Dhar
Asst. Professor, E&ECE Dept.
IIT Kharagpur, Kharagpur, India.
E mail ID: asd@ece.iitkgp.ernet.in



Declaration:

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

(JOYDEEP BHATTACHARYYA)