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Is there a Utility which converts ABEL or AHDL designs to Verilog or VHDL format
This is included as a utility in the xilinx tools and can
be found at %XILINX%/bin/nt/xport.exe.
It needs to be run via a DOS window.
But expect the output as a VHDL netlist. It is nothing you can comprehend. If you are intending it to just to synthesize it and test it without really looking at the VHDL generated, maybe XPORT is for you. I have used it for some legacy designs done in ABEL, and it would just error out on some abel files. so I had to do some changes manually.
If it is not too big of a design, it might be worth it to just convert from ABEL to VHDL by hand. You will have a clean design to start with , and you can run your test vectors to verfiy the design.
Never tried converting AHDL to VHDL. cant comment on it.
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