The comparison of Verilog with VHDL

Hi all,
can you give me a comparasion between Verilog and VHDL? advantages and disadvantages of them? Why in producing, they use Verilog instead VHDL
thanks in advance

Verilog v.s VHDL

SALAM,



BYE

Verilog v.s VHDL

Thanks SphinX
However,it was dead. I can't see anything
can anyone a new one

Re: Verilog v.s VHDL

Verilog and VHDL are both used EQUALLY in the industry.

Most silicon valley companies are currently using Verilog whereas VHDL is used for larger projects where a huge team is involved (most communication and defence related companies)...


Verilog was designed (initially) for verification whereas VHDL for documentation.

Verilog is still better than VHDL on the verification and simulation side (i use it to create my testbenches...whereas my modules are written in VHDL) .... whereas VHDL is a more detailed language (each module looks like a Document of Law).
Thus to improve verifcation in VHDL, VITAL(VHDL Initiative Toward Asic Libraries) was developed.

VHDL doesn't have a GATE-LEVEL or SWITCH-LEVEL like verilog.

Verilog is much more easier to use (it's format is very similar to C) whereas VHDL is somewhat more difficult syntaxwise (format similar to Pascal).

VHDL's complexity means that you define and document each and everything in detail. Thus it is good for large team projects...

Re: Verilog v.s VHDL

Hi All
I think there is an announcement about this topic made by the moderator.
Kindly try to read it again

Thanks

Verilog v.s VHDL

Pls. Read

Announcement: Verilog versus VHDL

Re: Verilog v.s VHDL

VHDL is better at following
1. Its difficult to bring in race condition in VHDL code. Except when you are
working with shared variables!

2. Its more structured. You dont have Records and Operator Overloading
concepts in Verilog.

Re: Verilog v.s VHDL

VHDL is more verbose, but Verilog is more consice, like C language.
It is said that you can model whatever you do in VHDL in Verilog and Vice Versa.
One thing that you don't have in Verilog,however, is Record and Operator Overloading, which is rarely used in modeling the circuites, at lease when you want to synthesize the circuite.

One thing that Verilog has and VHLD lacks, on the other hand, is the fork-join block. This is a very powerful construct in Verilog that lets you have nested parallel-sequential blocks inside each other. Sometimes this feature is called multi-threading. You cannot have this in VDHL unless you use explicit synchronizations between two different processes.

Verilog is going to be even more powerful with its new generation called SystemVerilog, which has more abstract constructs equivalent to Records. Just look systemVerilog on wikipedia website.

Re: Verilog v.s VHDL

What is the difference between VHDL and Verilog?


On the surface, not that much. Both are IEEE standards and are supported by all the major EDA vendors. Both can be used for designing ASICs and simulating systems. However, VHDL is altogether a grander language. Its support for system level modeling and simulation is far more comprehensive than Verilog. However, VHDL requires longer to learn and is not so amenable to quick-and-dirty coding. As a final thought many hardware engineers now have to know both languages due to the increasing use of IP (Intellectual Property) blocks, which may not be written in their "favourite" language

from:
https://www.doulos.com/knowhow/faq/vhdl_faq/