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Connecting two bidirectional ports in verilog

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bh_letters

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Hi,

I have two modules and each has a bidirectional (inout) port. Now I need to connect these ports. Both the modules use the same signal to determine the direction of data flow. If enable is low, module A acts as source and module B acts as destination. If enable is high, module B acts as source and module A acts as destination. Any suggestions please?

Thanks
 

Here is example how you do it in Verilog!
Hope this helps!

Code:
module A (inout_bus_a, en_a);
  inout [7:0] inout_bus_a;
  input en_a;
  
  
  reg [7:0] inout_bus_a_reg;
  assign inout_bus_a = (en_a) ? 'bz : inout_bus_a_reg;

 always () begin
    read_from_bus_data = inout_bus_a;
    ........
    ........
    inout_bus_a_reg = write_to_bus_data;
    ........
    ........
 end 
endmodule

module B (inout_bus_b, en_b);
  inout [7:0] inout_bus_b;
  input en_b;

  reg [7:0] inout_bus_b_reg;
  assign inout_bus_b = (en_b) ? inout_bus_b_reg : 'bz;

 always () begin
    read_from_bus_data = inout_bus_b;
    ........
    ........
    inout_bus_b_reg = write_to_bus_data;
    ........
    ........
 end
endmodule

module top;
  wire [7:0] inout_bus;
  reg en_b; // this needs to be driven by top

  A (inout_bus, en_b);
  B (inout_bus, en_b);

endmodule
 

Will this data transfer happen in one single clock pulse?

Added after 2 minutes:

Will this data transfer happen in one single clock pulse?

Added after 17 minutes:

Will this data transfer happen in one single clock pulse?

Added after 1 minutes:

Will this data transfer happen in one single clock pulse?
 

Hi,

The code which nand_gates has written seems to be fine. It is going to work for simulation purpose but i doubt it will work on the real FPGA. As I understand FPGAs internal architecture doesn't support High Impedence (1'bz) states meaning it can not have tri-state buffers in logic. Tri-state buffers can only be used on the FPGA top level in which case buffer is put in the IO block, not in the internal logic.

In this particular case, i think both the modules would have internally one input signal and one output signal driven out of bidirectional (inout) port. These two signals can directly be taken out of modules (as ports) and connected accordingly on the top level.

Regards.
 

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