Convert -A+jB to C+jD (loop gain of phase-locked loop)

I've got an equation that looks like:

A+jB
------
-C+jD

and I want it to look like

E+jF

Now I know that

A+jB
------
C+jD

can be changed to

(A+jB)(C-jD) =
----------------
(C+jD)(C-jD)

(AC+BD) + j(BC-AD)
--------------------------
C^2 + D^2

which then splits into

(AC+BD)
-----------
C^2 + D^2

+

j(BC-AD)
-----------
C^2 + D^2

which is the form E+jF that I wanted.

But how do I get it the fraction into a E+jF (or E-jF) form if the denominator is contains a negative real term?


The problem arises from being told (via "The Art of Electronics") that the loop gain of a phase-locked loop looks like:

A=

K* (that's simple multiplication, not congugate)

A+jB *
------
C+jD

1
---
jw

I'm beng told that all I need do is make this equation equal to one at a particular frequency, and I will have a stable (working!) phase-locked loop.

However, that last 1/jw term, when multiplied by the denominator C+jwD, produces a negative real term. The variable I want is a positive number, and the variable is contained in C. But yet, j*j=-1, and that produces a negative.

Maybe I'm making this harder than it is, or maybe I'm makng a mistake; I don't know which.

It seems to me that there was a way to get rid of a negative real, as I think I saw it years ago when I was studying using such math in school, but I just can't remember.

I'm really trying to get this, but I've tried several times to come up with the authors' resistor value, and it's just not workng. My latest attempt led me to this problem. I'm suspecting this guy used the LaPlace transform somewhere but didn't actually say it, and I'm hoping that's not the case, because I'm not seeing the application leading to the result of one.

(He says the VCO is an integrator, and LaPlace integration is division by s, which, in electronics, makes s=jw and, hence, produces the 1/jw factor that's throwing the wrench in the works of this, what should have been, simple complex algebra problem.)

....the preface of the book claims minimal math, but then this guy pulls out LaPlace and DOESN'T even try to explain it. Granted, I know generally about the LaPlace transform, as I've had ODE as well as some network analysis courses, but geez! It really looks like this guy's loop gain equation is a LaPlace transformation, but I don't see how an inverse LaPlace will help me solve this thing, and I at least am familiar. ...what about the poor schmuck who hasn't had this higher math??!

Anyway, if you can offer some assistance, I'd sure appreciate it.

P.S. I'm also looking for a schematic (a good one, not an esoteric half block diagram half schematic sort of thing) for the 4046 phase detector II, for I'm really striking out there also.

P.P.S. It's like designing a working phase-locked loop is some dark black magic secret or something the way these various authors really don't tell you much when in the beginning they say they will. So far I've found a "schematic" of the II detector from the manufacturer that isn't ...if you know what a J-K flip flop is..., a book that completely avoids the math of designing a suitable filter, and another book that supposedly designs a working loop, giving you the component values at the end, except the last one that'll complete the @%&^$* loop!! ...meanwhile deriding the poor schmuck who must resort to "cut and try." It's irritating. Then couple that with Multisim9, the folks who'll test their software before they sell it to you when pigs fly (a virtual PLL?? that has no VCOin? that asks for the cutoff frequency of the filter, when lead-lags, the most common PLL filter, have, technically, two?) ...

Please don't be scared to respond. I won't bite your head off. I'm just sayng these other things on the chance that someone else out there can relate.

------

Incidentally, the references referred to are

"Design of Phase-Locked Loop Circuits" Blacksburg -- no filter VALUE derivation, which would require actually designing one for the reader

"The Art of Electronics" Cambridge -- Great, if you're in the author's head

"CMOS Phase-Locked Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A" -- lovely esoteric phase detector II drawing -- J/K flip flops with only a D input (is that a J/K as a D? So why not say D dear author??)

Any 4046 datasheet -- useless - you might as well cut and try, just wing it. Hopefully it'll work right each time you need it to.

in the first part of ur question C+jD>>>> u can use C as either positive or negative the solution will be right

i.e if u have denominator -x+jy just multiply by -x-jy
u worte a very large question so i didnt read except this , hope this is what u want

Followup to my last...

For any out there who are trying to design the lag-lead loop filter for a CD4046, as I am, I recommend you check out one of the references I gave in my last: "CMOS Phase-Locked Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A" from Texas Instruments. It gives the equations and provides an example that produces values.

However, the author did make a couple of mistakes, so be aware:

1. His R4 value should be multiplied by 10 (he shifted a decimal place)
2. He claims to have used wf/wn=1/8, but he actually used wf/wn=0.1715, for 0.125 leads to the square root of a negative number.

So, the good news is, thanks to this TI author and Excel, I now have a spreadsheet that calculates the two resistor values for me given several variable parameters, a good starting point for the circuit.

Incidentally, as this is the math forum, the solution to my problem from the previous thread is to multiply by -C+jD/-C+jD. It just dawned on me several hours later.

Another followup...

Yes, as it turns out that author was using Laplace, but instead of using s, he used s=jω and didn't say what he did.

The equations of the various parts of the loop are (as I remember it -- the TI app note jumped to the end but did give correct eq's (they worked the 1st time!)):

Vd=Kd(Φo-Φi)
where Vd is the average dc from the phase detector (PD); Kd is the PD conversion gain (a constant); Φo and Φi are the phases of the output (from the VCO) and input signals

Vc=VdF(s)
where Vc is te control voltage to the VCO and F(s) is the transfer function after Laplace transformation (...which is why the Laplace transform of each section was needed...)

dΦo/dt=KoVc
where dΦo/dt is the rate of change of the VCO's output phase and Ko is the conversion gain (a constant) of the VCO

But what gets me is the Laplace transform of each section, and I'm still working that out. I'm seeing two integrations, one for the VCO but also one for the PD. ...gotta figure that out. suspect it has something to do with mathspeak.

For example, f(x) is not f times x; rather it's the function f at some x. I'm suspecting these books are flip-flopping, not remaining consistent. I'll figure it out.

Anyway, as I mentioned before, TI's equations for T1 and T2 (which you must find the equations for, solve for T1 and T2) do work. After solving them I dropped them into Excel and walla, played with the variables and produced an instantly (I thought I had a short at first!) locking PLL. ...now I just have to (just for personal satisfaction) figure out this math a little more.

If I get time (a tough thing), I'll come back here and post the T1 and T2 equations, just to save some poor shmuck out there the hassle I went through to get this far.