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the question for the xilinx analyze

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shenghuo

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the error information as followed:

logical net 'a_d' has multiple driver(s).

I'd like to ask how can i solve it? thanks for ur reply.
 

You have somethig like this in your program:
Code: 
.............
a_d <= signal1;
............
............
a_d <= signal2;
............
............
There are multiple assigments (drivers) to the same signal "a_d". You need to recode your program source.
bis
 

the error is inside port map.
such as a=>b in instant1,
c=>b in instant2,
because i want to connect a to signal b,b also to c.
but how to correct them?
 

Use MUX can solve your problem
 

I'm very grateful to get all ur helps.It is very encouraged when get a help in design difficulties.
 

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