Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to use output of c program in my vhdl program

Status
Not open for further replies.

subramanyam

Member level 3
Joined
Jul 29, 2006
Messages
56
Helped
9
Reputation
16
Reaction score
4
Trophy points
1,288
Location
bengaluru
Activity points
1,660
hii,

I am doing a project on memory controller in which i am trying to implement a design using fifos and FSMs . this design acts as an interface between the fast peripherals sending burst of data , and a slow memory.

i have implemented the design in VHDL. whenever the external device request read into memory, my design will put the address on the address bus of memory and, for write data it put the address on address bus and data on data bus .

my problem is, i want to implement the memory using linked lists in C language.
so whenever it takes that address and data how can i receive them into my vhdl testing program.

And how can i link these two, plz any one help me regarding this.

thank you,
subbu
 

(1) you can generate the data you want by C programming and then put them into you Testbench as TestVector
(2) If you're using unix, you can use script such as perl to link the two application by invoking system call.
 

using c program output into a file and you can read in vhdl usign file is in command .. thats easy way and generally we follow this way in industry..


Regards
Shankar
 

subramanyam said:
hii,

I am doing a project on memory controller in which i am trying to implement a design using fifos and FSMs . this design acts as an interface between the fast peripherals sending burst of data , and a slow memory.

i have implemented the design in VHDL. whenever the external device request read into memory, my design will put the address on the address bus of memory and, for write data it put the address on address bus and data on data bus .

my problem is, i want to implement the memory using linked lists in C language.
so whenever it takes that address and data how can i receive them into my vhdl testing program.

And how can i link these two, plz any one help me regarding this.

thank you,
subbu

Export your C output into one file. Call this file in VHDL code. Make this process automatic so it will do it countinuously. This is the standard way in simulation. Normally such method is used in Testbench for system level simulation.

for that you have to use following libraries:

USE IEEE.std_logic_textio.all;
USE std.textio.all;

and readline command in vhdl
 

there is a concept of FLI(Foriegn language interface) to link C model and vhdl model.
 

hys said:
Have a look at the following URL.... that may help u in using FLI.

h**p://www.lispworks.com/documentation/lwl42/FLI-U/html/fli.htm

Best Regards,
Harish
h**p://hdlplanet.tripod.com
h**p://groups.yahoo.com/group/hdlplanet

the FLI refered in link is related to LISP not VHDL. VHDL FLI is different...
It is part of VHDL standard and supported by vhdl simulators (or that support mix sim).


A quote from ModelSim® SE Foreign Language Interface
V e r s io n 6 . 1 e Pu b l i s h e d : M a r c h 2 0 0 6
FLI routines are C programming language functions that provide procedural access to
information within the HDL simulator. A user-written application can use these
functions to traverse the hierarchy of an HDL design, get information about and set the
values of VHDL objects in the design, get information about a simulation, and control (to
some extent) a simulation run. The header file mti.h externs all of the FLI functions and
types that can be used by an FLI application.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top