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need answer for verilog, why declare input as wire

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verilog no declare wire

in verilog HDL design, why declare input signals as wire type?
Such as:
-----------------------
module ex1 (a,b,c);
input a;
input b;
output c;

wire a; // why declare 'a' as wire type
wire b; // why declare 'b' as wire type
reg c;
...
----------------------
is there some special reason?
 

There is no need to declare inputs as wire, by default they r wires, which acts as input signals to the logic which is going to be done inside the module
 

I can't understand why Verilog distinguish "wire" and "reg". In fact, "reg"s are not always registers. They should be declared as "reg"s just because they will be used in "always", but "always" doesn't mean registers.

Then what's the purpose of "reg" definition?
 

reg is used to store values whereas wire used to transfer values from one port to another.wire does not store the values as done by the reg.
 

Reg is storage element and wire is for passing info.
 

if reg variables are used in "always" without edge-controll sensitive list, then there is no storage elements.
 

eruisi said:
if reg variables are used in "always" without edge-controll sensitive list, then there is no storage elements.
Click to expand...
No, even if your "always" without edge-controll sensitive list,your can still get a latch sometime.
 

You are right, but in general, this is not the right way we write the code.

When design a simple combinational circuit, you have two ways:
assign a = .... (wire)
always ... (reg)

but they are equivelant. No registers or latches are used.

beta0 said:
eruisi said:
if reg variables are used in "always" without edge-controll sensitive list, then there is no storage elements.
Click to expand...
No, even if your "always" without edge-controll sensitive list,your can still get a latch sometime.
Click to expand...
 

input just can be in RHS, so it/s wire
 

it is already wire
it is register when it is specified in particular to be so
 

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