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PORT CHANGE INTERRUPT IN PIC 16FXXX

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creative_35

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include 16fxxx

I have problem in port change enable configuration while simulating this routine in mblab.
I configured RB4 as changing port and when firing RB4, it jumps to ISR and never returns from ISR routine. I don't know why. any of you had such problems? pls help me.


Code: 
	list      p=16f628            ; list directive to define processor
	#include <p16f628.inc>        ; processor specific variable definitions
	
	__CONFIG _CP_OFF & _WDT_ON & _BODEN_ON & _PWRTE_ON & _ER_OSC_CLKOUT & _MCLRE_ON & _LVP_ON


;***** VARIABLE DEFINITIONS
w_temp        EQU     0x70        ; variable used for context saving 
status_temp   EQU     0x71        ; variable used for context saving

;**********************************************************************
		ORG     0x000             ; processor reset vector
		goto    main              ; go to beginning of program

;****************ISR ROUTINE**********************************
		ORG     0x004             ; interrupt vector location
		movwf   w_temp            ; save off current W register contents
		movf	STATUS,w          ; move status register into W register
		movwf	status_temp       ; save off contents of STATUS register


	BANKSEL INTCON
	bcf INTCON,RBIF

		movf    status_temp,w     ; retrieve copy of STATUS register
		movwf	STATUS            ; restore pre-isr STATUS register contents
		swapf   w_temp,f
		swapf   w_temp,w          ; restore pre-isr W register contents
		retfie                    ; return from interrupt
:***********************************************************************
MAIN
	BANKSEL CMCON
	movlw 7h
	movwf CMCON
	BANKSEL PORTB
	clrf PORTB
	clrf PORTA
	BANKSEL TRISB
	movlw 0x10
	movwf TRISB
	clrf TRISA

START
	BANKSEL INTCON
	bsf INTCON ,GIE
	bcf INTCON,RBIF
	bsf INTCON,RBIE
	goto $

		END
 

Hi creative_35

You will find your retfie is actioned but the interupt flag RBIF is set again on the line following bcf INTCON,RBIF.

Explanation:
When interupted by int-on-change you will need to clear the mismatch condition on PORTB by a read or write of the PORTB - then RBIF can be cleared. Clearing the RBIF flag alone does not clear the mismatch condition.

If the mismatch condition continues, the RBIF flag will be set on the next Q1 machine cycle and another interupt will occur - and again and again......

The compare is between last PORTB Read and portb scan every Q1 machine cycle.

Note: As any instruction with a file as a destination has a read-modify-write action such that a write to PORTB will provide the READ necessary to end the mismatch condition.

Refer to the 877A data sheet - PortB description

Special Note:
PORTB(7:4) data is latched-in every Q1 machine cycle.
If you have fast changes (spike/glitch) on PORTB these may be detected by int-on-change but not read from the pins or thay may be missed altogether.
The minimum pulse time is 1 instruction cycle to be sure of capture.

Mismatch clearing is conducted during Q3 machine cycle.

hope this helps Polymath
 
Thankyou verymuch Polymath.
I have added bcf PORTB,4 along with clearing of rbif and it's working.
 

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